Altera Cyclone V User Manual page 83

Chapter 5: IP Core Interfaces
Power Management Signals
Table 5–18
Table 5–18. Power Management Capabilities Register
31 24 22 16
data
rsvd
register
Table 5–19
Capabilities register.
Table 5–19. Power Management Capabilities Register Field Descriptions
Bits Field
[31:24]
Data register
[22:16]
reserved
[15]
PME_status
[14:13]
data_scale
[12:9]
data_select
[8]6
PME_EN
[7:2]
reserved
[1:0]
PM_state
Figure 5–19
the Hard IP receives the PME_turn_off message which causes pme_to_sr to assert.
Then, the Application Layer sends the PME_to_ack message to the Root Port by
asserting pme_to_cr.
Figure 5–19. pme_to_sr and pme_to_cr in an Endpoint IP core
November 2011 Altera Corporation
shows the layout of the Power Management Capabilities register.
15 14
PME_status data_scale
describes the use of the various fields of the Power Management
This field indicates in which power states a function can assert the PME# message.
When set to 1, indicates that the function would normally assert the PME# message
independently of the state of the PME_en bit.
This field indicates the scaling factor when interpreting the value retrieved from the data
register. This field is read-only.
This field indicates which data should be reported through the data register and the
data_scale field.
1: indicates that the function can assert PME#
0: indicates that the function cannot assert PME#
Specifies the power management state of the operating condition being described. The
following encodings are defined:
2b'00 D0
■
2b'01 D1
■
2b'10 D2
■
2b'11 D3
■
A device returns 2b'11 in this field and Aux or PME Aux in the type register to specify
the D3-Cold PM state. An encoding of 2b'11 along with any other type register value
specifies the D3-Hot state.
illustrates the behavior of pme_to_sr and pme_to_cr in an Endpoint. First,
pme_to_sr
hard
IP
pme_to_cr
13 12 9
data_select PME_EN
Description
—
—
8 7 2 1
rsvd PM_state
Cyclone V Hard IP for PCI Express
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5–31
0