Error Reporting And Data Poisoning - Altera Cyclone V User Manual

Chapter 12: Error Handling

Error Reporting and Data Poisoning

Table 12–4. Errors Detected by the Transaction Layer (Part 3 of 3)
Error
Malformed TLP
(continued)
Note to Table 12–4:
(1) Considered optional by the PCI Express Base Specification Revision
Error Reporting and Data Poisoning
How the Endpoint handles a particular error depends on the configuration registers
of the device.
f
Refer to the
and logging for an Endpoint.
The Hard IP block implements data poisoning, a mechanism for indicating that the
data associated with a transaction is corrupted. Poisoned TLPs have the
error/poisoned bit of the header set to 1 and observe the following rules:
■ Received poisoned TLPs are sent to the Application Layer and status bits are
automatically updated in the Configuration Space.
■ Received poisoned Configuration Write TLPs are not written in the Configuration
Space.
The Configuration Space never generates a poisoned TLP; the error/poisoned bit
■
of the header is always set to 0.
Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status
register.
Table 12–5. Parity Error Conditions
Status Bit
Detected parity error (status register bit 15)
Master data parity error (status register bit 8)
Poisoned packets received by the Hard IP block are passed to the Application Layer.
Poisoned transmit TLPs are similarly sent to the link.
November 2011 Altera Corporation
Type
A request specifies an address/length combination that causes a
■
memory space access to exceed a 4 KByte boundary. The Hard IP
block checks for this violation, which is considered optional by the
PCI Express specification.
Uncorrectable
Messages, such as Assert_INTX, Power Management, Error
■
(fatal)
Signaling, Unlock, and Set Power Slot Limit, must be transmitted
across the default traffic class.
The Hard IP block deletes the malformed TLP; it is not presented to the
Application Layer.
PCI Express Base Specification 2.1
Table 12–5 lists the conditions that cause parity errors.
Set when any received TLP is poisoned.
This bit is set when the command register parity enable bit is set and one of
the following conditions is true:
The poisoned bit is set during the transmission of a Write Request TLP.
■
The poisoned bit is set on a received completion TLP.
■
Description
2.1.
for a description of the device signaling
Conditions
12–5
Cyclone V Hard IP for PCI Express
User Guide