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MAX 10
Altera MAX 10 FPGA Development Board Manuals
Manuals and User Guides for Altera MAX 10 FPGA Development Board. We have
2
Altera MAX 10 FPGA Development Board manuals available for free PDF download: User Manual
Altera MAX 10 User Manual (87 pages)
Clocking and PLL
Brand:
Altera
| Category:
Motherboard
| Size: 1 MB
Table of Contents
Table of Contents
2
MAX 10 Clocking and PLL Overview
5
Clock Networks Overview
5
Internal Oscillator Overview
5
Plls Overview
5
MAX 10 Clocking and PLL Architecture and Features
7
Clock Networks Architecture and Features
7
Global Clock Networks
7
Clock Pins Introduction
7
Clock Resources
8
Global Clock Network Sources
8
Global Clock Control Block
10
Global Clock Network Power down
12
Clock Enable Signals
13
Internal Oscillator Architecture and Features
14
Plls Architecture and Features
14
PLL Architecture
14
PLL Features
16
PLL Locations
16
Clock Pin to PLL Connections
18
PLL Counter to GCLK Connections
18
PLL Control Signals
19
Clock Feedback Modes
20
PLL External Clock Output
23
ADC Clock Input from PLL
25
Spread-Spectrum Clocking
25
PLL Programmable Parameters
25
Clock Switchover
28
PLL Cascading
32
PLL Reconfiguration
32
MAX 10 Clocking and PLL Design Considerations
35
Clock Networks Design Considerations
35
Guideline: Clock Enable Signals
35
Guideline: Connectivity Restrictions
35
Internal Oscillator Design Considerations
36
Guideline: Connectivity Restrictions
36
Plls Design Considerations
36
Guideline: PLL Control Signals
36
Guideline: Self-Reset
36
Guideline: Output Clocks
37
Guideline: PLL Cascading
37
Guideline: Clock Switchover
38
Guideline: .Mif Streaming in PLL Reconfiguration
39
Guideline: Scandone Signal for PLL Reconfiguration
39
MAX 10 Clocking and PLL Implementation Guides
40
ALTCLKCTRL IP Core
40
IP Catalog and Parameter Editor
40
Specifying IP Core Parameters and Options
41
Files Generated for Altera IP Cores (Legacy Parameter Editor)
43
ALTPLL IP Core
44
IP Catalog and Parameter Editor
45
Specifying IP Core Parameters and Options
46
Files Generated for Altera IP Cores (Legacy Parameter Editor)
56
ALTPLL_RECONFIG IP Core
57
IP Catalog and Parameter Editor
57
Specifying IP Core Parameters and Options
58
Files Generated for Altera IP Cores (Legacy Parameter Editor)
59
Obtaining the Resource Utilization Report
60
Internal Oscillator IP Core
60
IP Catalog and Parameter Editor
61
Specifying IP Core Parameters and Options
62
Files Generated for Altera IP Cores (Legacy Parameter Editor)
63
ALTCLKCTRL IP Core References
65
ALTCLKCTRL Parameters
65
ALTCLKCTRL Ports and Signals
66
ALTPLL IP Core References
68
ALTPLL Parameters
68
Operation Modes Parameter Settings
68
PLL Control Signals Parameter Settings
69
Programmable Bandwidth Parameter Settings
69
Clock Switchover Parameter Settings
70
PLL Dynamic Reconfiguration Parameter Settings
71
Dynamic Phase Configuration Parameter Settings
71
Output Clocks Parameter Settings
72
ALTPLL Ports and Signals
73
ALTPLL_RECONFIG IP Core References
78
ALTPLL_RECONFIG Parameters
78
ALTPLL_RECONFIG Ports and Signals
79
ALTPLL_RECONFIG Counter Settings
84
Internal Oscillator IP Core References
86
Document Revision History for MAX 10 Clocking and PLL User Guide
87
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Altera MAX 10 User Manual (68 pages)
Analog to Digital Converter
Brand:
Altera
| Category:
Media Converter
| Size: 1 MB
Table of Contents
Table of Contents
2
MAX 10 Analog to Digital Converter Overview
4
ADC Block Counts in MAX 10 Devices
5
ADC Channel Counts in MAX 10 Devices
6
MAX 10 ADC Vertical Migration Support
7
MAX 10 Single or Dual Supply Devices
8
MAX 10 ADC Conversion
8
MAX 10 ADC Architecture and Features
10
MAX 10 ADC Hard IP Block
10
ADC Block Locations
11
Single or Dual ADC Devices
13
ADC Analog Input Pins
14
ADC Prescaler
14
ADC Clock Sources
14
ADC Voltage Reference
15
ADC Temperature Sensing Diode
15
ADC Sequencer
17
ADC Timing
18
Altera Modular ADC and Altera Modular Dual ADC IP Cores
18
Altera Modular ADC IP Core Configuration Variants
19
Altera Modular ADC and Altera Modular Dual ADC IP Cores Architecture
24
Altera ADC HAL Driver
29
ADC Toolkit for Testing ADC Performance
29
ADC Logic Simulation Output
29
Fixed ADC Logic Simulation Output
30
User-Specified ADC Logic Simulation Output
31
MAX 10 ADC Design Considerations
33
Guidelines: ADC Ground Plane Connection
33
Guidelines: Board Design for Power Supply Pin and ADC Ground ( REFGND )
33
Guidelines: Board Design for Analog Input
34
Guidelines: Board Design for ADC Reference Voltage Pin
36
MAX 10 ADC Implementation Guides
37
Creating MAX 10 ADC Design
38
Customizing and Generating Altera Modular ADC IP Core
39
Parameters Settings for Generating ALTPLL IP Core
39
Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core
41
Completing ADC Design
44
Altera Modular ADC and Altera Modular Dual ADC IP Cores References
45
Altera Modular ADC Parameters Settings
46
Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
50
Altera Modular Dual ADC Parameters Settings
52
Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping
56
Valid ADC Sample Rate and Input Clock Combination
57
Altera Modular ADC and Altera Modular Dual ADC Interface Signals
57
Command Interface of Altera Modular ADC and Altera Modular Dual ADC
57
Response Interface of Altera Modular ADC and Altera Modular Dual ADC
58
Threshold Interface of Altera Modular ADC and Altera Modular Dual ADC
59
CSR Interface of Altera Modular ADC and Altera Modular Dual ADC
60
IRQ Interface of Altera Modular ADC and Altera Modular Dual ADC
60
Peripheral Clock Interface of Altera Modular ADC and Altera Modular Dual ADC
61
Peripheral Reset Interface of Altera Modular ADC and Altera Modular Dual ADC
61
ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC
61
ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC
62
Altera Modular ADC Register Definitions
62
Sequencer Core Registers
62
Sample Storage Core Registers
63
ADC HAL Device Driver for Nios II Gen 2
64
MAX 10 Analog to Digital Converter User Guide Archives
65
Document Revision History for MAX 10 Analog to Digital Converter User Guide
66
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