Altera Cyclone V User Manual page 62

5–10
Table 5–4. 64- or 128-Bit Avalon-ST TX Datapath (Part 3 of 3)
Signal
tx_cred_fchipcons
tx_cred_fc_infinite
tx_cred_hdrfccp
tx_cred_hdrfcnp
tx_cred_hdrfcp
ko_cpl_spc_header
ko_cpl_spc_data
Note to Table 5–4:
(1) To be Avalon-ST compliant, your application have a readyLatency of 1 or 2 cycles.
Cyclone V Hard IP for PCI Express
Avalon-ST
Width Dir
Type
Asserted for 1 cycle each time the Hard IP consumes a
credit. The 6 bits of this vector correspond to the following
6 types of credit types:
■
■
component
■
6 O
specific
■
■
■
During a single cycle, the Hard IP can consume either a
single header credit or both a header and a data credit.
When asserted, indicates that the corresponding credit
type has infinite credits available and does not need to
calculate credit limits. The 6 bits of this vector correspond
to the following 6 types of credit types:
■
component
6 O
■
specific
■
■
■
■
Header credit limit for the FC completions. Each credit is 20
component
8 O
bytes.
specific
Header limit for the non-posted requests. Each credit is 20
component
8 O
bytes.
specific
Header credit limit for the FC posted writes. Each credit is
component
8 O
20 bytes.
specific
The Application Layer can use this signal to build circuitry
to prevent RX buffer overflow for completion headers.
Endpoints must advertise infinite space for completion
component
8 O headers; however, RX buffer space is finite.
specific
ko_cpl_spc_header is a static signal that indicates the
total number of completion headers that can be stored in
the RX buffer.
The Application Layer can use this signal to build circuitry
to prevent RX buffer overflow for completion data.
Endpoints must advertise infinite space for completion
data; however, RX buffer space is finite.
component
12 O ko_cpl_spc_data is a static signal that reflects the total
specific
number of 16 byte completion data units that can be stored
in the completion RX buffer. The total read data from all
outstanding MRd requests must be less than this value to
prevent RX FIFO overflow.
Description
[5]: posted headers
[4]: posted data
[3]: non-posted header
[2]: non-posted data
[1]: completion header
[0]: completion data
[5]: posted headers
[4]: posted data
[3]: non-posted header
[2]: non-posted data
[1]: completion header
[0]: completion data
November 2011 Altera Corporation
Chapter 5: IP Core Interfaces
Avalon-ST TX Interface