Altera Cyclone V User Manual page 23

Chapter 2: Getting Started
Qsys Design Flow
4. Specify the Link settings listed in
Table 2–11. Link Tab
Link port number
Slot clock configuration
5. Specify the Slot settings listed in
Table 2–12. Link Tab
Use slot register
Data link layer active reporting
Surprise down reporting
Slot clock configuration
6. Specify the Power Management settings listed
Table 2–13. Power Management Parameters
Endpoint L0s acceptable exit latency
Endpoint L1 acceptable latency
7. Specify the BAR settings for Func0 listed in
Table 2–14. Base Address Registers for Func0
BAR0 Type
BAR0 Size
BAR1 Type
BAR1 Size
BAR2 Type
BAR2 Size
8. You can leave Func0 BAR3 through Func0 BAR5 and the Func0 Expansion ROM
Disabled.
9. Under the Base and Limit Registers heading, disable both the Input/Output and
Prefetchable memory options. (These options are for Root Ports.)
10. Specify the Device ID Registers for Func0 listed in
Table 2–15. Device Identification Registers for Func0 (Part 1 of 2)
Vendor ID
Device ID
Revision ID
November 2011 Altera Corporation
Parameter
Parameter
Parameter
Parameter
Register Name
Table 2–11.
Table 2–12.
Leave this option off.
0
0
0
in.Table 2–13.
Maximum of 64 ns
Maximum of 1 µs
Table 2–14.
64-bit prefetchable memory
256 MBytes - 28 bits
Disabled
N/A
32-bit non-prefetchable memory
1 KByte - 10 bits
Table
Value
0x00000000
0x00000001
0x00000001
2–11
Value
1
Enabled
Value
Value
Value
2–15.
Cyclone V Hard IP for PCI Express
User Guide