Altera Cyclone V User Manual page 59

Chapter 5: IP Core Interfaces
Avalon-ST RX Interface
Figure 5–6
for a four dword header with non-qword addresses with a 64-bit bus. Note that the
address of the first dword is 0x4. The address of the first enabled byte is 0x6. This
example shows one valid word in the first dword, as indicated by the rx_st_be signal.
Figure 5–6. 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLP with Non-Qword Address
coreclkout
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_bar[7:0]
rx_st_be[7:4]
rx_st_be[3:0]
Note to Figure 5–6:
(1) rx_st_be[7:4] corresponds to rx_st_data[63:32]. rx_st_be[3:0] corresponds to rx_st_data[31:0].
Figure 5–7
backpressures the Cyclone V Hard IP for PCI Express by deasserting rx_st_ready.
The rx_st_valid signal must deassert within three cycles after rx_st_ready is
deasserted. In this example, rx_st_valid is deasserted in the next cycle. rx_st_data is
held until the Application Layer is able to accept it.
Figure 5–7. 64-Bit Application Layer Backpressures Transaction Layer
coreclkout
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_bardec[7:0]
rx_st_be[7:4]
rx_st_be[3:0]
November 2011 Altera Corporation
shows the mapping of Avalon-ST RX packet to PCI Express TLPs for TLPs
header1 header3
header0 header2
10
illustrates the timing of the RX interface when the Application Layer
header1 header3
header0 header2
10
data0 data2
data1
C F
F
data0 data2
data1
C F
F
Cyclone V Hard IP for PCI Express
5–7
(1)
User Guide