Altera Cyclone V User Manual page 112

10–2
Figure 10–2
vector enable bit. A global Application Layer interrupt enable can also be
implemented instead of this per vector MSI.
Figure 10–2. Example Implementation of the MSI Handler Block
There are 32 possible MSI messages. The number of messages requested by a
particular component does not necessarily correspond to the number of messages
allocated. For example, in
allocated two. In this case, you must design the Application Layer to use only two
allocated messages.
Figure 10–3. MSI Request Example
Cyclone V Hard IP for PCI Express
illustrates a possible implementation of the MSI handler block with a per
Vector 0
app_int_en0
R/W
app_int_sts0
Vector 1
app_int_en1
R/W
app_int_sts1
Figure
Endpoint
8 Requested
2 Allocated
app_int_sts
app_msi_req0
MSI
Arbitration
app_msi_req1
10–3, the Endpoint requests eight MSIs but is only
Root Complex
Root
Port
Interrupt
Block
Interrupt Register
Chapter 10: Interrupts
Interrupts for Endpoints
msi_enable & Master Enable
app_msi_req
app_msi_ack
CPU
November 2011 Altera Corporation