Altera Cyclone V User Manual page 78

5–26
Table 5–14. Configuration Space Register Descriptions (Part 3 of 3)
Width
Register
cfg_pr_bas
cfg_pr_lim
cfg_pmcsr
cfg_msixcsr
cfg_msicsr
cfg_tcvcmap
cfg_busdev
Table 5–15
Cyclone V Hard IP for PCI Express
Dir
The upper 44 bits of the prefetchable base registers of the
44 O Type1 Configuration Space. This register is only available in
Root Port mode.
The upper 44 bits of the prefetchable limit registers of the Type1
44 O
Configuration Space. Available in Root Port mode.
cfg_pmcsr[31:16] is Power Management Control and
32 O
cfg_pmcsr[15:0]is the Power Management Status register.
16 O MSI-X message control.
MSI message control. Refer to
16 O
register.
Configuration traffic class (TC)/virtual channel (VC) mapping.
The Application Layer uses this signal to generate a TLP
mapped to the appropriate channel based on the traffic class of
the packet.
cfg_tcvcmap[2:0]: Mapping for TC0 (always 0).
cfg_tcvcmap[5:3]: Mapping for TC1.
24 O
cfg_tcvcmap[8:6]: Mapping for TC2.
cfg_tcvcmap[11:9]: Mapping for TC3.
cfg_tcvcmap[14:12]: Mapping for TC4.
cfg_tcvcmap[17:15]: Mapping for TC5.
cfg_tcvcmap[20:18]: Mapping for TC6.
cfg_tcvcmap[23:21]: Mapping for TC7.
13 O Bus/Device Number captured by or programmed in the Hard IP.
shows the layout of the Configuration MSI Control Status register.
Transaction Layer Configuration Space Signals
Description
Table 5–15 for the fields of this
November 2011 Altera Corporation
Chapter 5: IP Core Interfaces
Register
Reference
Table 6–3 on
page 6–2
0x024 and
Table 3–7 on
page 3–8
Prefetchable
memory
Table 6–3 on
page 6–2
0x024 and
Table 3–7 on
page 3–8
Prefetchable
memory
Table 6–6 on
page 6–4
0x07C
Table 6–5 on
page 6–3
0x068
Table 6–4 on
page 6–3
0x050
—
Table A–5 on
page A–2
0x08