Altera Stratix FPGA Development Kit Manuals

Manuals and User Guides for Altera Stratix FPGA Development Kit. We have 1 Altera Stratix FPGA Development Kit manual available for free PDF download: Handbook

Altera Stratix Handbook (572 pages)

Volume 2

Brand: Altera | Category: Motherboard | Size: 6 MB

Table of Contents
3
Chapter Revision Dates

13
About this Handbook

15
- How to Find Information
  15
- How to Contact Altera
  15
- Typographic Conventions
  16
Section I. Clock Management

17
- Revision History
  17
- Introduction
  19
- Enhanced Plls
  23
  - Clock Multiplication & Division
    27
  - External Clock Outputs
    28
  - Clock Feedback
    32
  - Phase Shifting
    32
  - Lock Detect
    33
  - Programmable Duty Cycle
    34
  - General Advanced Clear & Enable Control
    34
  - Programmable Bandwidth
    36
  - Clock Switchover
    43
  - Spread-Spectrum Clocking
    43
  - PLL Reconfiguration
    48
  - Enhanced PLL Pins
    48
- Fast Plls
  49
  - Clock Multiplication & Division
    52
  - External Clock Outputs
    52
  - Phase Shifting
    53
  - Programmable Duty Cycle
    54
  - Control Signals
    54
  - Pins
    55
- Clocking
  57
- Board Layout
  68
  - Vcca & Gnda
    68
  - Vccg & Gndg
    70
  - External Clock Output Power
    71
  - Guidelines
    74
- Conclusion
  74
Chapter 1. General-Purpose Plls in Stratix & Stratix GX Devices

17
Section II. Memory

75
- Revision History
  75
Chapter 2. Trimatrix Embedded Memory Blocks in Stratix & Stratix GX Devices

77
- Introduction
  77
- Trimatrix Memory
  77
  - Clear Signals
    79
  - Parity Bit Support
    79
  - Byte Enable Support
    80
- Using Trimatrix Memory
  83
- Clock Modes
  92
  - Independent Clock Mode
    92
  - Input/Output Clock Mode
    94
  - Read/Write Clock Mode
    97
  - Single-Port Mode
    99
- Designing with Trimatrix Memory
  99
- Read-During-Write Operation at the same Address
  101
  - Same-Port Read-During-Write Mode
    101
  - Mixed-Port Read-During-Write Mode
    102
- Conclusion
  103
Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices

105
- Introduction
  105
- External Memory Standards
  105
  - Ddr Sdram
    105
  - Rldram II
    108
  - Qdr & Qdrii Sram
    110
  - Zbt Sram
    112
- DDR Memory Support Overview
  114
  - DDR Memory Interface Pins
    115
  - DQS Phase-Shift Circuitry
    119
  - DDR Registers
    124
  - Pll
    131
- Conclusion
  131
Section III. I/O Standards

133
- Revision History
  133
Chapter 4. Selectable I/O Standards in Stratix & Stratix GX Devices

133
Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices

181
- Introduction
  181
- Stratix I/O Banks
  181
  - Stratix Differential I/O Standards
    182
  - Stratix Differential I/O Pin Location
    185
- Principles of SERDES Operation
  186
- Using SERDES to Implement DDR
  193
- Using SERDES to Implement SDR
  194
- Differential I/O Interface & Fast Plls
  196
  - Clock Input & Fast PLL Output Relationship
    198
  - Fast PLL Specifications
    200
  - High-Speed Phase Adjust
    201
  - Counter Circuitry
    202
  - Fast PLL SERDES Channel Support
    203
  - Advanced Clear & Enable Control
    205
- Receiver Data Realignment
  205
- Source-Synchronous Timing Budget
  210
  - Differential Data Orientation
    210
  - Differential I/O Bit Position
    211
  - Timing Definition
    212
  - Input Timing Waveform
    219
  - Output Timing
    220
  - Receiver Skew Margin
    220
  - Switching Characteristics
    222
  - Timing Analysis
    222
- SERDES Bypass DDR Differential Signaling
  222
- High-Speed Interface Pin Locations
  225
- Differential I/O Termination
  226
- Board Design Consideration
  230
- Software Support
  231
  - Differential Pins in Stratix
    231
  - Fast Plls
    232
  - LVDS Receiver Block
    240
  - LVDS Transmitter Module
    245
  - SERDES Bypass Mode
    250
- Summary
  255
Section IV. Digital Signal Processing (DSP)

257
- Revision History
  257
Chapter 6. DSP Blocks in Stratix & Stratix GX Devices

259
- Introduction
  259
- DSP Block Overview
  260
- Architecture
  263
  - Multiplier Block
    263
  - Adder/Output Block
    267
  - Routing Structure & Control Signals
    270
- Operational Modes
  276
  - Simple Multiplier Mode
    276
  - Multiply Accumulator Mode
    280
  - Two-Multiplier Adder Mode
    281
  - Four-Multiplier Adder Mode
    282
- Software Support
  286
- Conclusion
  286
Chapter 7. Implementing High Performance DSP Functions

287
In Stratix & Stratix GX Devices

287
- Introduction
  287
- Stratix & Stratix GX DSP Block Overview
  287
- Trimatrix Memory Overview
  290
- DSP Function Overview
  291
- Finite Impulse Response (FIR) Filters
  291
  - FIR Filter Background
    292
  - Basic FIR Filter
    293
  - Time-Domain Multiplexed FIR Filters
    299
  - Polyphase FIR Interpolation Filters
    303
  - Polyphase FIR Decimation Filters
    310
  - Complex FIR Filter
    317
- Infinite Impulse Response (IIR) Filters
  320
  - IIR Filter Background
    320
  - Basic IIR Filters
    322
  - Butterworth IIR Filters
    325
- Matrix Manipulation
  331
  - Background on Matrix Manipulation
    331
  - Two-Dimensional Filtering & Video Imaging
    332
- Discrete Cosine Transform (DCT)
  338
  - DCT Background
    338
  - 2-D DCT Algorithm
    339
- Arithmetic Functions
  345
  - Background
    345
  - Arithmetic Function Implementation
    346
  - Arithmetic Function Implementation Results
    348
  - Arithmetic Function Design Example
    348
- Conclusion
  348
- References
  349
Section V. IP & Design Considerations

351
- Revision History
  351
Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices

353
- Introduction
  353
  - Related Links
    353
- 10-Gigabit Ethernet
  353
- Interfaces
  357
  - Xsbi
    357
  - Xgmii
    365
  - Xaui
    371
- I/O Characteristics for XSBI, XGMII & XAUI
  374
  - Software Implementation
    374
  - AC/DC Specifications
    374
  - 10-Gigabit Ethernet MAC Core
    376
  - Conclusion
    377
Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices

379
- Introduction
  379
  - System Topology
    381
  - Interface Implementation in Stratix & Stratix GX Devices
    383
  - AC Timing Specifications
    388
  - Electrical Specifications
    390
  - Software Implementation
    391
  - Conclusion
    391
Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices

393
- Introduction
  393
- General Architecture
  393
  - Logic Elements
    394
  - Multitrack Interconnect
    395
  - Directdrive Technology
    396
  - Architectural Element Names
    397
- Trimatrix Memory
  400
  - Same-Port Read-During-Write Mode
    402
  - Mixed-Port Read-During-Write Mode
    403
  - Memory Megafunctions
    404
  - FIFO Conditions
    405
  - Design Migration Mode in Quartus II Software
    405
- DSP Block
  408
  - DSP Block Megafunctions
    408
- Plls & Clock Networks
  410
  - Clock Networks
    410
  - Plls
    411
- I/O Structure
  417
  - External RAM Interfacing
    417
  - I/O Standard Support
    418
  - High-Speed Differential I/O Standards
    418
  - Altlvds Megafunction
    421
- Configuration
  422
  - Configuration Speed & Schemes
    422
  - Remote Update Configuration
    423
  - JTAG Instruction Support
    423
- Conclusion
  424
Section VI. System Configuration & Upgrades

425
- Revision History
  426
Chapter 11. Configuring Stratix & Stratix GX Devices

427
- Introduction
  427
- Device Configuration Overview
  428
  - MSEL[2..0] Pins
    429
  - VCCSEL Pins
    429
  - PORSEL Pins
    431
  - Nio_Pullup Pins
    431
  - TDO & Nceo Pins
    432
- Configuration File Size
  432
- Altera Configuration Devices
  433
- Configuration Schemes
  433
  - PS Configuration
    433
  - FPP Configuration
    447
  - PPA Configuration
    456
  - JTAG Programming & Configuration
    462
  - JTAG Programming & Configuration of Multiple Devices
    465
  - Configuration with Jrunner Software Driver
    467
  - Jam STAPL Programming & Test Language
    468
- Configuring Using the Microblaster Driver
  477
- Device Configuration Pins
  477
Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices

487
- Introduction
  487
- Remote Configuration Operation
  487
  - Remote System Configuration Modes
    489
  - Remote System Configuration Components
    491
- Quartus II Software Support
  498
  - Altremote_Update Megafunction
    500
  - Remote Update WYSIWYG ATOM
    503
- Using Enhanced Configuration Devices
  505
  - Local Update Programming File Generation
    507
  - Remote Update Programming File Generation
    518
- Combining MAX Devices & Flash Memory
  528
- Using an External Processor
  529
- Conclusion
  530
Section VII. PCB Layout Guidelines

531
- Revision History
  531
Chapter 13. Package Information for Stratix Devices

533
- Introduction
  533
- Device & Package Cross Reference
  533
- Thermal Resistance
  534
- Package Outlines
  535
Chapter 14. Designing with 1.5-V Devices

549
- Introduction
  549
- Power Sequencing & Hot Socketing
  549
- Using Multivolt I/O Pins
  550
- Voltage Regulators
  551
  - Linear Voltage Regulators
    553
  - Switching Voltage Regulators
    555
  - Maximum Output Current
    556
  - Selecting Voltage Regulators
    557
  - Voltage Divider Network
    558
  - 1.5-V Regulator Circuits
    558
- V Regulator Application Examples
  567
  - Synchronous Switching Regulator Example
    568
- Board Layout
  569
  - Split-Plane Method
    571
- Conclusion
  571
- References
  572

Altera Categories

Motherboard Microcontrollers Computer Hardware Transceiver Media Converter

More Altera Manuals

Altera Stratix FPGA Development Kit Manuals

Altera Stratix Handbook (572 pages)

Table of Contents

Chapter Revision Dates

About this Handbook

Section I. Clock Management

Chapter 1. General-Purpose Plls in Stratix & Stratix GX Devices

Section II. Memory

Chapter 2. Trimatrix Embedded Memory Blocks in Stratix & Stratix GX Devices

Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices

Section III. I/O Standards

Chapter 4. Selectable I/O Standards in Stratix & Stratix GX Devices

Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices

Section IV. Digital Signal Processing (DSP)

Chapter 6. DSP Blocks in Stratix & Stratix GX Devices

Chapter 7. Implementing High Performance DSP Functions

In Stratix & Stratix GX Devices

Section V. IP & Design Considerations

Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices

Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices

Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices

Section VI. System Configuration & Upgrades

Chapter 11. Configuring Stratix & Stratix GX Devices

Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices

Section VII. PCB Layout Guidelines

Chapter 13. Package Information for Stratix Devices

Chapter 14. Designing with 1.5-V Devices

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