Fpga Programming From Flash Memory; Flash Programming Over Usb Interface - Altera Cyclone III Reference Manual

Table 2–7. JTAG Settings
Number Description
5 External USB Blaster (3),
MAX II target device only
Note to Table 2–7:
(1) The nomenclature SW3.1 is used to indicate board reference SW3, position 1; similarly SW1.5 is used to indicate
board reference SW1, position 5.
(2) Requires USB cable plugged into board reference J3.
(3) Requires external USB Blaster or equivalent plugged into board reference J14 (PCB bottom).
Altera Corporation
March 2008
Note (1)
FPGA HSMA
Bypass Bypass
(SW3.1) (SW3.2)
X X

FPGA Programming from Flash Memory

On either power-up or by pressing the RESET_CONFIG or
FACTORY_CONFIG push button, the MAX II CPLD device's PFL
megafunction will configure the Cyclone III FPGA from flash memory.
The PFL megafunction reads 16-bit data from the flash memory and
converts it to passive serial format. The data is written to the Cyclone III
device's dedicated DCLK and D0 configuration pins at 12 MHz.
FPGA configuration from flash memory can be sourced from one of eight
images. The image is selected by the PGM_CONFIG_SELECT rotary
switch, board reference SW5. The rotary switch has 16 positions, but only
the first eight are used. The positions correspond to an offset in flash
memory that the PFL is directed to for FPGA configuration data.
1
Board reference SW1 position 5 (SW1.5), labeled MAX0, must be
in the open position (off) for this feature to be enabled. If the
SW1 switch is in the open position, the PFL megafunction in the
MAX II CPLD is disabled.

Flash Programming over USB Interface

The flash memory can be programmed at any time the board is
powered up using the USB 2.0 interface and the Quartus II Programmer's
JTAG mode.
The development kit implements the Altera parallel flash loader (PFL)
megafunction for flash programming. The PFL is a block of logic that is
programmed into an Altera programmable logic device (FPGA or CPLD).
The PFL functions as a utility for writing to a compatible flash device. The
development kit ships with a pre-built PFL design called
Reference Manual
HSMB MAX
Enable
Bypass Enable
(SW1.5
(SW3.3) (SW3.4)
MAX0)
X X X
Cyclone III Development Board
Board Components
PFL
Device Select
(DEV_SEL)
Jumper, J6
On
2–19