Altera Stratix III Manuals

Manuals and User Guides for Altera Stratix III. We have 4 Altera Stratix III manuals available for free PDF download: Device Handbook, Design Manuallines, Using Manual, Getting Started User Manual

Altera Stratix III Device Handbook (904 pages)

Brand: Altera | Category: Microcontrollers | Size: 13 MB

Table of Contents

3
- Chapter Revision Dates
  13
- About this Handbook
  15
  - How to Contact Altera
    15
  - Typographic Conventions
    15
- Section I. Device Core
  17
- Chapter 1. Stratix III Device Family Overview
  
  19
  - Introduction
    19
    
    Features
    20
  - Architecture Features
    23
    
    Logic Array Blocks and Adaptive Logic Modules
    23
    
    Multitrack Interconnect
    24
    
    Trimatrix Embedded Memory Blocks
    25
    
    DSP Blocks
    25
    
    Clock Networks and Plls
    26
    
    I/O Banks and I/O Structure
    27
    
    External Memory Interfaces
    27
    
    High Speed Differential I/O Interfaces with DPA
    28
    
    Hot Socketing and Power-On Reset
    28
    
    Configuration
    29
    
    Remote System Upgrades
    30
    
    IEEE 1149.1 (JTAG) Boundary Scan Testing
    30
    
    Design Security
    30
    
    SEU Mitigation
    31
    
    Programmable Power
    31
    
    Signal Integrity
    32
  - Reference and Ordering Information
    32
    
    Software
    32
    
    Ordering Information
    33
  - Referenced Documents
    34
  - Document Revision History
    34
- Chapter 2 . Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
  
  35
  - Introduction
    35
  - Logic Array Blocks
    35
    
    LAB Interconnects
    37
    
    LAB Control Signals
    38
  - Adaptive Logic Modules
    39
    
    ALM Operating Modes
    42
    
    Register Chain
    54
    
    ALM Interconnects
    56
    
    Clear and Preset Logic Control
    57
    
    LAB Power Management Techniques
    57
  - Conclusion
    58
  - Referenced Documents
    58
  - Document Revision History
    58
- Chapter 3. Multitrack Interconnect in Stratix III Devices
  
  59
  - Introduction
    59
  - Row Interconnects
    59
  - Column Interconnects
    61
  - Memory Block Interface
    66
  - DSP Block Interface
    68
  - I/O Block Connections to Interconnect
    71
  - Conclusion
    72
  - Document Revision History
    73
- Chapter 4 . Trimatrix Embedded Memory Blocks in Stratix III Devices
  
  75
  - Introduction
    75
  - Overview
    75
    
    Trimatrix Memory Block Types
    77
    
    Parity Bit Support
    77
    
    Byte Enable Support
    77
    
    Packed Mode Support
    79
    
    Address Clock Enable Support
    79
    
    Mixed Width Support
    81
    
    Asynchronous Clear
    81
    
    Error Correction Code (ECC) Support
    82
  - Memory Modes
    83
    
    Single Port RAM
    84
    
    Simple Dual-Port Mode
    86
    
    True Dual-Port Mode
    89
    
    Shift-Register Mode
    91
    
    ROM Mode
    92
    
    FIFO Mode
    93
  - Clocking Modes
    93
    
    Independent Clock Mode
    93
    
    Input/Output Clock Mode
    94
    
    Read/Write Clock Mode
    94
    
    Single Clock Mode
    94
  - Design Considerations
    94
    
    Selecting Trimatrix Memory Blocks
    94
    
    Conflict Resolution
    95
    
    Read During Write
    95
    
    Power-Up Conditions and Memory Initialization
    98
    
    Power Management
    98
  - Conclusion
    98
  - Document Revision History
    99
- Chapter 5 . DSP Blocks in Stratix III Devices
  
  101
  - Introduction
    101
  - DSP Block Overview
    101
  - Simplified DSP Operation
    103
  - Operational Modes Overview
    109
  - DSP Block Resource Descriptions
    110
    
    Input Registers
    111
    
    Multiplier and First-Stage Adder
    115
    
    Pipeline Register Stage
    116
    
    Second-Stage Adder
    116
    
    Round and Saturation Stage
    117
    
    Second Adder and Output Registers
    117
    
    36-Bit Multiplier
    122
    
    Double Multiplier
    123
    
    Two-Multiplier Adder Sum Mode
    125
    
    18 × 18 Complex Multiply
    129
    
    Four-Multiplier Adder
    131
    
    Multiply Accumulate Mode
    133
    
    Shift Modes
    134
    
    Rounding and Saturation Mode
    136
    
    DSP Block Control Signals
    139
  - Application Examples
    141
    
    FIR Example
    141
    
    FFT Example
    148
  - Software Support
    149
  - Conclusion
    149
  - Referenced Documents
    149
  - Document Revision History
    150
- Chapter 6. Clock Networks and Plls in Stratix III Devices
  
  151
  - Introduction
    151
  - Clock Networks in Stratix III Devices
    152
    
    Clock Input Connections to Plls
    162
    
    Clock Output Connections
    163
    
    Clock Source Control for Plls
    164
    
    Clock Control Block
    166
    
    Clock Enable Signals
    170
    
    Stratix III PLL Hardware Overview
    174
    
    Stratix III PLL Software Overview
    178
    
    Clock Feedback Modes
    182
    
    Clock Multiplication and Division
    188
    
    Post-Scale Counter Cascading
    189
    
    Programmable Duty Cycle
    190
    
    PLL Control Signals
    190
    
    Clock Switchover
    191
    
    Programmable Bandwidth
    197
    
    Phase-Shift Implementation
    200
    
    PLL Reconfiguration
    202
    
    Spread-Spectrum Tracking
    214
    
    PLL Specifications
    214
  - Conclusion
    214
  - Referenced Documents
    214
  - Document Revision History
    215
  - Section II. I/O Interfaces
    217
- Chapter 7. Stratix III Device I/O Features
  
  219
  - Introduction
    219
  - Stratix III I/O Standards Support
    220
    
    I/O Standards and Voltage Levels
    221
  - Stratix III I/O Banks
    223
    
    Modular I/O Banks
    226
  - Stratix III I/O Structure
    232
    
    3.3-V I/O Interface
    233
    
    External Memory Interfaces
    235
    
    High-Speed Differential I/O with DPA Support
    235
    
    Programmable Current Strength
    236
    
    Programmable Slew Rate Control
    237
    
    Programmable Delay
    238
    
    Open-Drain Output
    238
    
    Bus Hold
    239
    
    Programmable Pull-Up Resistor
    239
    
    Programmable Pre-Emphasis
    240
    
    Programmable Differential Output Voltage
    240
    
    Multivolt I/O Interface
    240
  - OCT Support
    241
    
    LVDS Input On-Chip Termination (R D )
    247
  - OCT Calibration
    248
    
    OCT Calibration Block Location
    248
    
    OCT Calibration Block Modes of Operation
    251
  - Termination Schemes for I/O Standards
    255
    
    Single-Ended I/O Standards Termination
    255
    
    Differential I/O Standards Termination
    257
  - Design Considerations
    264
    
    I/O Termination
    264
    
    I/O Banks Restrictions
    265
    
    I/O Placement Guidelines
    266
  - Conclusion
    268
  - Referenced Documents
    268
- Chapter 8. External Memory Interfaces in Stratix III Devices
  
  268
  - Introduction
    271
  - Memory Interfaces Pin Support
    276
    
    Data and Data Clock/Strobe Pins
    276
    
    Optional Parity, DM, Bwsn, ECC and QVLD Pins
    288
    
    Address and Control/Command Pins
    289
    
    Memory Clock Pins
    290
  - Stratix III External Memory Interface Features
    292
    
    DQS Phase-Shift Circuitry
    302
    
    DQS Logic Block
    302
    
    Leveling Circuitry
    306
    
    Dynamic On-Chip Termination Control
    308
    
    I/O Element (IOE) Registers
    309
    
    IOE Features
    313
    
    Pll
    315
  - Conclusion
    315
  - Referenced Documents
    316
  - Document Revision History
    316
- Chapter 9 . High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
  
  317
  - Introduction
    317
  - I/O Banks
    318
  - LVDS Channels
    319
  - Differential Transmitter
    320
    
    Receiver Data Realignment Circuit (Bit Slip)
    325
    
    Dynamic Phase Aligner (DPA)
    326
    
    Soft-CDR Mode
    327
    
    Synchronizer
    328
  - Programmable Pre-Emphasis and Programmable VOD
    328
  - Differential I/O Termination
    329
  - Left/Right Plls (Pll_Lx/ Pll_Rx)
    330
  - Clocking
    331
    
    Source-Synchronous Timing Budget
    332
    
    Differential Data Orientation
    333
    
    Differential I/O Bit Position
    333
    
    Receiver Skew Margin for Non-DPA
    335
  - Differential Pin Placement Guidelines
    337
    
    Guidelines for DPA-Enabled Differential Channels
    337
    
    Guidelines for DPA-Disabled Differential Channels
    345
  - Referenced Documents
    350
  - Document Revision History
    350
  - Section III. Hot Socketing, Configuration, Remote Upgrades, and Testing
    351
- Chapter 10 . Hot Socketing and Power-On Reset in Stratix III Devices
  
  353
  - Introduction
    353
  - Stratix III Hot-Socketing Specifications
    354
    
    Devices Can be Driven before Power-Up
    354
    
    I/O Pins Remain Tri-Stated During Power-Up
    354
    
    Insertion or Removal of a Stratix III Device from a Powered-Up System
    354
  - Power-On Reset Circuitry
    356
  - Power-On Reset Specifications
    358
  - Conclusion
    359
  - Document Revision History
    359
  - Referenced Documents
    359
- Chapter 11 . Configuring Stratix III Devices
  
  361
  - Introduction
    361
    
    Configuration Devices
    361
    
    Configuration Schemes
    361
  - Configuration Features
    363
    
    Configuration Data Decompression
    364
    
    Design Security Using Configuration Bitstream Encryption
    368
    
    Remote System Upgrade
    368
    
    Power-On Reset Circuit
    368
    
    VCCPGM Pins
    369
    
    CCPD Pins
    369
    
    FPP Configuration Using a MAX II Device as an External Host
    370
    
    FPP Configuration Using a Microprocessor
    381
  - Fast Active Serial Configuration (Serial Configuration Devices)
    382
    
    Estimating Active Serial Configuration Time
    387
    
    Programming Serial Configuration Devices
    388
  - Passive Serial Configuration
    391
    
    PS Configuration Using a MAX II Device as an External Host
    391
    
    PS Configuration Using a Microprocessor
    399
    
    PS Configuration Using a Download Cable
    399
  - JTAG Configuration
    403
    
    Jam STAPL
    410
  - Device Configuration Pins
    410
  - Conclusion
    420
  - Document Revision History
    422
- Chapter 12 . Remote System Upgrades with Stratix III Devices
  
  423
  - Introduction
    423
    
    Enabling Remote Update
    426
    
    Configuration Image Types
    427
  - Remote System Upgrade Mode
    428
    
    Overview
    428
    
    Remote Update Mode
    428
  - Dedicated Remote System Upgrade Circuitry
    430
    
    Remote System Upgrade Registers
    432
    
    Remote System Upgrade State Machine
    435
    
    User Watchdog Timer
    436
    
    Altremote_Update Megafunction
    437
  - Conclusion
    438
  - Document Revision History
    438
  - Referenced Documents
    438
- Chapter 13 . IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
  
  439
  - Introduction
    439
  - IEEE Std. 1149.1 BST Architecture
    440
  - IEEE Std. 1149.1 Boundary-Scan Register
    442
    
    Boundary-Scan Cells of a Stratix III Device I/O Pin
    444
  - IEEE Std. 1149.1 BST Operation Control
    448
    
    SAMPLE/PRELOAD Instruction Mode
    450
    
    EXTEST Instruction Mode
    452
    
    BYPASS Instruction Mode
    454
    
    IDCODE Instruction Mode
    455
    
    USERCODE Instruction Mode
    456
    
    CLAMP Instruction Mode
    456
    
    HIGHZ Instruction Mode
    456
  - I/O Voltage Support in JTAG Chain
    456
  - IEEE Std. 1149.1 BST Circuitry
    458
  - IEEE Std. 1149.1 BST Circuitry (Disabling)
    459
  - IEEE Std. 1149.1 BST for Configured Devices
    459
  - IEEE Std. 1149.1 BST Guidelines
    460
  - Boundary-Scan Description Language (BSDL) Support
    461
  - Conclusion
    461
  - Referenced Documents
    461
  - Section IV. Design Security & Single Event Upset (SEU) Mitigation
    464
- Chapter 14. Design Security in Stratix III Devices
  
  465
  - Introduction
    465
  - Stratix III Security Protection
    466
    
    Security against Copying
    466
    
    Security against Reverse Engineering
    466
    
    Security against Tampering
    466
  - AES Decryption Block
    467
  - Flexible Security Key Storage
    467
  - Stratix III Design Security Solution
    468
  - Security Modes Available
    469
  - Supported Configuration Schemes
    470
  - Conclusion
    473
  - Referenced Documents
    473
  - Document Revision History
    473
- Chapter 15. SEU Mitigation in Stratix III Devices
  
  475
  - Introduction
    475
  - Configuration Error Detection
    476
  - User Mode Error Detection
    476
    
    Automated Single Event Upset Detection
    480
    
    Critical Error Detection
    480
  - Error Detection Pin Description
    481
    
    CRC_ERROR Pin
    481
    
    CRITICAL ERROR Pin
    482
  - Error Detection Block
    482
    
    Error Detection Registers
    483
  - Error Detection Timing
    485
    
    Software Support
    486
  - Recovering from CRC Errors
    488
  - Conclusion
    488
  - Referenced Documents
    488
  - Document Revision History
    488
  - Section V. Power and Thermal Management
    489
- Chapter 16 . Programmable Power and Temperature Sensing Diode in Stratix III Devices
  
  491
  - Introduction
    491
  - Stratix III Power Technology
    492
    
    Selectable Core Voltage
    492
    
    Programmable Power Technology
    493
    
    Relationship between Selectable Core Voltage and Programmable Power Technology
    494
  - Temperature Sensing Diode
    496
    
    External Pin Connections
    497
  - Conclusion
    497
  - Referenced Documents
    497
  - Document Revision History
    498
  - Section VI. Packaging Information
    499
- Chapter 17. Stratix III Device Packaging Information
  
  501
  - Introduction
    501
  - Thermal Resistance
    502
  - Package Outlines
    502
  - Referenced Documents
    502
  - Document Revision History
    502
Table of Contents

505
- Chapter Revision Dates
  507
- About this Handbook
  509
  - How to Contact Altera
    509
  - Typographic Conventions
    509
- Section I. DC & Switching Characteristics of Stratix III Devices
  511
- Chapter 1. Stratix III Device Datasheet: DC and Switching Characteristics
  513
  - Electrical Characteristics
    513
    
    Operating Conditions
    513
    
    Power Consumption
    525
  - Switching Characteristics
    526
    
    Core Performance Specifications
    526
    
    Periphery Performance
    532
  - I/O Timing
    539
    
    Timing Model
    539
    
    Preliminary and Final Timing
    540
    
    I/O Timing Measurement Methodology
    540
    
    I/O Default Capacitive Loading
    545
    
    Maximum I/O Toggle Rate
    546
    
    Programmable IOE Delay
    566
    
    Programmable Output Buffer Delay
    566
    
    User I/O Pin Timing
    567

Altera Stratix III Design Manuallines (71 pages)

Brand: Altera | Category: Microcontrollers | Size: 0 MB

Considerations

18
"Making Fpga Pin Assignments," on Page

28
- Making FPGA Pin Assignments
  28
- And
  29
  - Early Pin Planning and I/O Assignment Analysis
    29
- I/O Features and Pin Connections
  30
- Clock and PLL Selection
  37
- PLL Design Guidelines
  39
- Simultaneous Switching Noise
  41

Altera Stratix III Getting Started User Manual (36 pages)

Brand: Altera | Category: Microcontrollers | Size: 2 MB

Table of Contents
3
Chapter 1. About this Kit

5
- Introduction
  5
- Kit Features
  5
Chapter 2. Getting Started

7
- Introduction
  7
- Before You Begin
  7
- Check the Kit Contents
  7
- Inspect the Board
  8
- Hardware Requirements
  8
- Software Requirements
  9
- References
  9
Chapter 3. Software Installation

11
Chapter 4. DSP Development Kit Hardware Setup

17
- Introduction
  17
- Requirements
  17
- Powering up the Board
  17
- Configuring the FPGA
  22
Chapter 5. Factory Designs

23
Appendix A. Programming the Flash Device

29
- Overview
  29
- Creating a Flash File
  29
- Parallel Flash Loader Instantiation
  31
- Programming the Flash Device
  31
- Restoring the Factory Design to the Flash Device
  33
- Additional Information
  35
- Revision History
  35
- How to Contact Altera
  35
- Typographic Conventions
  36

Altera Stratix III Using Manual (59 pages)

Using DDR3 SDRAM in Devices

Brand: Altera | Category: Motherboard | Size: 2 MB

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Altera Stratix III Manuals

Altera Stratix III Device Handbook (904 pages)

Table of Contents

Table of Contents

Chapter 1. Stratix III Device Family Overview

Chapter 2 . Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices

Chapter 3. Multitrack Interconnect in Stratix III Devices

Chapter 4 . Trimatrix Embedded Memory Blocks in Stratix III Devices

Chapter 5 . DSP Blocks in Stratix III Devices

Chapter 6. Clock Networks and Plls in Stratix III Devices

Chapter 7. Stratix III Device I/O Features

Chapter 8. External Memory Interfaces in Stratix III Devices

Chapter 9 . High-Speed Differential I/O Interfaces and DPA in Stratix III Devices

Chapter 10 . Hot Socketing and Power-On Reset in Stratix III Devices

Chapter 11 . Configuring Stratix III Devices

Chapter 12 . Remote System Upgrades with Stratix III Devices

Chapter 13 . IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices

Chapter 14. Design Security in Stratix III Devices

Chapter 15. SEU Mitigation in Stratix III Devices

Chapter 16 . Programmable Power and Temperature Sensing Diode in Stratix III Devices

Chapter 17. Stratix III Device Packaging Information

Table of Contents

Altera Stratix III Design Manuallines (71 pages)

Table of Contents

Considerations

"Making Fpga Pin Assignments," on Page

Altera Stratix III Getting Started User Manual (36 pages)

Table of Contents

Chapter 1. About this Kit

Chapter 2. Getting Started

Chapter 3. Software Installation

Chapter 4. DSP Development Kit Hardware Setup

Chapter 5. Factory Designs

Appendix A. Programming the Flash Device

Altera Stratix III Using Manual (59 pages)

Table of Contents

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