Factory-Programmed Reference Design - Altera Nios Cyclone II Edition Reference Manual

Overview
f
Figure 1–1. Nios Development Board, Cyclone II Edition Block Diagram
50MHz Oscillator
5.0 V Regulators
JTAG Connector
Mictor Connector
Proto 1 Expansion
Prototype Connector
Compact Flash
Proto 2 Expansion
Prototype Connector
Push-button
Switches (4)
User LEDs (8)
Dual Seven-Segment Display
Factory-
Programmed
Reference
Design
1–2
Nios Development Board Cyclone II Edition
See the Nios II Development Kit, Getting Started User Guide for instructions
on setting up the Nios development board and installing Nios II
development tools.
Figure 1–1shows a block diagram of the Nios development board.
Vccint 1.2-V
Vccio 3.3-V
27
Cyclone II
EP2C35
FPGA
41
4
8
16
When power is applied to the board, on-board logic configures the FPGA
using hardware configuration data stored in flash memory. After
successful configuration, the Nios II processor design in the FPGA wakes
up and begins executing boot code from flash memory.
The board is factory-programmed with a default reference design. This
reference design is a web server that delivers web pages via the Ethernet
port. For further information on the default reference design, refer to
Appendix B: Connecting to the Board via Ethernet.
Reference Manual
16 Mbyte DDR SDRAM
2 Mbyte SSRAM
EPCS64 Configuration
Device
Configuration
Controller
16 Mbyte Flash Memory
Ethernet RJ45
MAC/PHY Connector
PMC Connector
RS-232
Altera Corporation
May 2007