A/D Control Register (Adcr) - Renesas H8 Series Hardware Manual

Section 16 A/D Converter
16.3.3

A/D Control Register (ADCR)

ADCR enables A/D conversion started by an external trigger signal.
Bit Bit Name
7 TRGE
6 to 4 —
3, 2 —
1 —
0 —
Rev. 3.00 Sep. 14, 2006 Page 278 of 408
REJ09B0105-0300
Initial
Value R/W Description
0 R/W Trigger Enable
A/D conversion is started at the falling edge and the rising
edge of the external trigger signal (ADTRG) when this bit
is set to 1.
The selection between the falling edge and rising edge of
the external trigger pin (ADTRG) conforms to the WPEG5
bit in the interrupt edge select register 2 (IEGR2)
All 1 — Reserved
These bits are always read as 1.
All 0 R/W Reserved
Although these bits are readable/writable, they should not
be set to 1.
1 R/W Reserved
This bit is always read as 1.
0 R/W Reserved
Although this bit is readable/writable, it should not be set
to 1.