Renesas H8 Series Hardware Manual page 403

16-bit single-chip microcomputer
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Instruction Mnemonic
INC
INC.B Rd
INC.W #1/2, Rd
INC.L #1/2, ERd
JMP
JMP @ERn
JMP @aa:24
JMP @@aa:8
JSR
JSR @ERn
JSR @aa:24
JSR @@aa:8
LDC
LDC #xx:8, CCR
LDC Rs, CCR
LDC@ERs, CCR
LDC@(d:16, ERs), CCR
LDC@(d:24,ERs), CCR
LDC@ERs+, CCR
LDC@aa:16, CCR
LDC@aa:24, CCR
MOV
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
MOV.B @(d:16, ERs), Rd
MOV.B @(d:24, ERs), Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @Erd
MOV.B Rs, @(d:16, ERd)
MOV.B Rs, @(d:24, ERd)
MOV.B Rs, @-ERd
MOV.B Rs, @aa:8
Instruction
Branch
Fetch
Addr. Read
I
J
1
1
1
2
2
2
1
2
2
2
1
1
1
2
3
5
2
3
4
1
1
1
2
4
1
1
2
3
1
2
4
1
1
Stack
Byte Data
Operation
Access
K
L
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 3.00 Sep. 14, 2006 Page 373 of 408
Appendix
Word Data
Internal
Access
Operation
M
N
2
2
2
1
1
1
1
2
1
1
2
2
REJ09B0105-0300

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