Timer Control Register W (Tcrw) - Renesas H8 Series Hardware Manual

Section 12 Timer W
12.3.2

Timer Control Register W (TCRW)

TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer
output levels.
Bit Bit Name
7 CCLR
6 CKS2
5 CKS1
4 CKS0
3 TOD
2 TOC
1 TOB
Rev. 3.00 Sep. 14, 2006 Page 164 of 408
REJ09B0105-0300
Initial
Value R/W Description
0 R/W Counter Clear
The TCNT value is cleared by compare match A when
this bit is 1. When it is 0, TCNT operates as a free-
running counter.
0 R/W Clock Select 2 to 0
0 R/W Select the TCNT clock source.
000: Internal clock: counts on φ
0 R/W
001: Internal clock: counts on φ/2
010: Internal clock: counts on φ/4
011: Internal clock: counts on φ/8
1XX: Counts on rising edges of the external event (FTCI)
When the internal clock source (φ) is selected, subclock
sources are counted in subactive and subsleep modes.
0 R/W Timer Output Level Setting D
Sets the output value of the FTIOD pin until the first
compare match D is generated.
0: Output value is 0*
1: Output value is 1*
0 R/W Timer Output Level Setting C
Sets the output value of the FTIOC pin until the first
compare match C is generated.
0: Output value is 0*
1: Output value is 1*
0 R/W Timer Output Level Setting B
Sets the output value of the FTIOB pin until the first
compare match B is generated.
0: Output value is 0*
1: Output value is 1*