A/D Control/Status Register (Adcsr); Table 16.2 Analog Input Channels And Corresponding Addr Registers - Renesas H8 Series Hardware Manual

Section 16 A/D Converter
Therefore, byte access to ADDR should be done by reading the upper byte first then the lower
one. ADDR is initialized to H'0000.

Table 16.2 Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel
AN0
AN1
AN2
AN3
16.3.2

A/D Control/Status Register (ADCSR)

ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Bit Bit Name
7 ADF
6 ADIE
5 ADST
Rev. 3.00 Sep. 14, 2006 Page 276 of 408
REJ09B0105-0300
A/D Data Register to Be Stored Results of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD
Initial
Value R/W Description
0 R/W A/D End Flag
[Setting conditions]
•
•
[Clearing condition]
•
0 R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled by
ADF when 1 is set
0 R/W A/D Start
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when conversion on
the specified channel is complete. In scan mode,
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software, a reset,
or a transition to standby mode.
When A/D conversion ends in single mode
When A/D conversion ends on all the channels
selected in scan mode
When 0 is written after reading ADF = 1