Renesas H8 Series Hardware Manual page 431

Item
Figure 2.1 Memory Map (2)
Table 3.1 Exception Sources
and Vector Address
Figure 5.1 Block Diagram of
Clock Pulse Generators
5.2.1 RC Control Register
(RCCR)
5.2.2 RC Trimming Data
Protect Register
(RCTRMDPR)
Page Revision (See Manual for Details)
13
H'0000
H'0045
H'0046
48
Relative Module
IIC2*
Timer B1*
Note: * Available for the H8/36912 Group only.
69
71
Bit Bit Name
1 RCPSC1
0 RCPSC0
73
Bit Bit Name
4 TRMDRWE Trimming Date Register Write Enable
H8/36911
H8/36901
(Masked ROM version (Masked ROM version
(under planning))
H'0000
Interrupt vector
H'0045
H'0046
Exception Sources
IIC_2 transmit data empty
IIC_2 transmit end
IIC_2 receive error
Timer B1 overflow
System
OSC φ
1
OSC
clock correction
OSC
2
oscillator
R
OSC
R
On-chip Clock
OSC
R
OSC
divider
oscillator
R
OSC
Description
Division Ratio Select for On-chip Oscillator
The division ratio of R
OSC
rewriting this bit.
These bits can be written to only when the CKSTA
bit in CKCSR is 0.
0X: R (not divided)
OSC
10: R /2
OSC
11: R /4
OSC
Description
This register can be written to when the LOCKDW
bit is 0 and this bit is 1.
[Setting condition]
•
When writing 0 to the WRI bit while writing 1 to
the TRMDRWE bit while the PRWE bit is 1
[Clearing conditions]
•
Reset
•
When writing 0 to the WRI bit and writing 0 to
the TRMDRWE bit while the PRWE bit is 1
Rev. 3.00 Sep. 14, 2006 Page 401 of 408
H8/36900
(under planning))
Interrupt vector
Duty
circuit
/2
/4
changes right after
REJ09B0105-0300