Renesas H8 Series Hardware Manual page 12

3.2.4 Interrupt Enable Register 2 (IENR2) .................................................................. 51
3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 52
3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 53
3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 53
3.3 Reset Exception Handling .................................................................................................. 54
3.4 Interrupt Exception Handling ............................................................................................. 55
3.4.1 External Interrupts .............................................................................................. 55
3.4.2 Internal Interrupts ............................................................................................... 56
3.4.3 Interrupt Handling Sequence .............................................................................. 57
3.4.4 Interrupt Response Time..................................................................................... 59
3.5 Usage Notes ........................................................................................................................ 61
3.5.1 Interrupts after Reset........................................................................................... 61
3.5.2 Notes on Stack Area Use .................................................................................... 61
3.5.3 Notes on Rewriting Port Mode Registers ........................................................... 61
Section 4 Address Break ..................................................................................... 63
4.1 Register Descriptions.......................................................................................................... 64
4.1.1 Address Break Control Register (ABRKCR) ..................................................... 64
4.1.2 Address Break Status Register (ABRKSR) ........................................................ 66
4.1.3 Break Address Registers (BARH, BARL).......................................................... 66
4.1.4 Break Data Registers (BDRH, BDRL) ............................................................... 66
4.2 Operation ............................................................................................................................ 67
Section 5 Clock Pulse Generators ....................................................................... 69
5.1 Features............................................................................................................................... 70
5.2 Register Descriptions.......................................................................................................... 71
5.2.1 RC Control Register (RCCR) ............................................................................. 71
5.2.2 RC Trimming Data Protect Register (RCTRMDPR).......................................... 72
5.2.3 RC Trimming Data Register (RCTRMDR) ........................................................ 73
5.2.4 Clock Control/Status Register (CKCSR)............................................................ 74
5.3 System Clock Select Operation .......................................................................................... 75
5.3.1 Clock Control Operation..................................................................................... 76
5.3.2 Clock Change Timing......................................................................................... 78
5.4 Trimming of On-chip Oscillator Frequency ....................................................................... 80
5.5 External Oscillators ............................................................................................................ 82
5.5.1 Connecting Crystal Resonator ............................................................................ 82
5.5.2 Connecting Ceramic Resonator .......................................................................... 83
5.5.3 External Clock Input Method.............................................................................. 83
5.6 Prescaler.............................................................................................................................. 83
5.6.1 Prescaler S .......................................................................................................... 83
Rev. 3.00 Sep. 14, 2006 Page x of xxviii