Figure 12.3 Periodic Counter Operation; Figure 12.4 0 And 1 Output Example (Toa = 0, Tob = 1) - Renesas H8 Series Hardware Manual

Periodic counting operation can be performed when GRA is set as an output compare register and
bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the
IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt
request is generated. TCNT continues counting from H'0000. Figure 12.3 shows periodic
counting.
TCNT value
GRA
H'0000
CTS bit
IMFA
By setting a general register as an output compare register, compare match A, B, C, or D can
cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle.
Figure 12.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1
output is selected for compare match A, and 0 output is selected for compare match B. When
signal is already at the selected output level, the signal level does not change at compare match.
TCNT value
H'FFFF
GRA
GRB
H'0000
FTIOA
FTIOB

Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)

Figure 12.3 Periodic Counter Operation

No change
Flag cleared
by software
No change No change
No change
Rev. 3.00 Sep. 14, 2006 Page 173 of 408
Section 12 Timer W
Time
Time
REJ09B0105-0300