Figure 14.1 Block Diagram Of Sci3 - Renesas H8 Series Hardware Manual

16-bit single-chip microcomputer

Hide thumbs Also See for H8 Series:

Table of Contents

Section 14 Serial Communication Interface 3 (SCI3)

Clocked synchronous mode

• Data length: 8 bits

• Receive error detection: Overrun errors

filter circuit

Receive shift register

Receive data register

Transmit shift register

Transmit data register

Serial mode register

Serial control register 3

Serial status register

Bit rate register

Bit rate counter

Sampling mode register

Rev. 3.00 Sep. 14, 2006 Page 198 of 408

REJ09B0105-0300

Transmit/receive

control circuit

Figure 14.1 Block Diagram of SCI3

Internal clock (φ/64,φ/16, φ/4, φ)

Interrupt request

(TEI, TXI, RXI, ERI)