Renesas H8 Series Hardware Manual page 433

Item
13.2.1 Timer Control/Status
Register WD (TCSRWD)
14.8.2 Mark State and Break
Sending
2
15.3.5 I C Bus Status
Register (ICSR)
Figure 15.15 Receive Mode
Operation Timing
15.7 Usage Notes
16.3.1 A/D Data Registers A
to D (ADDRA to ADDRD)
Figure 17.2 Block Diagram
of Power-On Reset Circuit
and Low-Voltage Detection
Circuit
20.3 Electrical
Characteristics (Masked
ROM Version)
Page Revision (See Manual for Details)
192
Bit Bit Name Description
4 TCSRWE Timer Control/Status Register WD Write Enable
236 Replaced
251
Bit Bit Name Description
3 STOP
265
SCL
SDA
(Input)
MST
272 Added
There are four 16-bit read-only ADDR registers; ......
276
Therefore, byte access to ADDR should be done by reading the
upper byte first then the lower one. ADDR is initialized to H'0000.
287
331 20.3 Electrical Characteristics (Masked ROM Version) [Preliminary]
The guarantee value for the electrical characteristics of masked ROM
version is preliminary.
20.3.1 Power Supply Voltage and Operating Ranges
The WDON and WRST bits can be written when
the TCSRWE bit is set to 1.
When writing data to this bit, the value for bit 5
must be 0.
Stop Condition Detection Flag
[Setting conditions]
•
In master mode, when a stop condition is
detected after frame transfer
•
In slave mode, when a stop condition is
detected after the general call address or
the first byte slave address, next to
detection of start condition, accords with the
address set in SAR
......
7 8
Bit 6 Bit 7
RES
C RES
Rev. 3.00 Sep. 14, 2006 Page 403 of 408
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Bit 0 Bit 1
REJ09B0105-0300