Renesas H8 Series Hardware Manual page 18

Section 16 A/D Converter ................................................................................. 273
16.1 Features............................................................................................................................. 273
16.2 Input/Output Pins.............................................................................................................. 275
16.3 Register Description ......................................................................................................... 275
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .......................................... 275
16.3.2 A/D Control/Status Register (ADCSR) ............................................................ 276
16.3.3 A/D Control Register (ADCR) ......................................................................... 278
16.4 Operation .......................................................................................................................... 279
16.4.1 Single Mode...................................................................................................... 279
16.4.2 Scan Mode ........................................................................................................ 279
16.4.3 Input Sampling and A/D Conversion Time ...................................................... 280
16.4.4 External Trigger Input Timing.......................................................................... 281
16.5 A/D Conversion Accuracy Definitions ............................................................................. 282
16.6 Usage Notes ...................................................................................................................... 284
16.6.1 Permissible Signal Source Impedance .............................................................. 284
16.6.2 Influences on Absolute Accuracy ..................................................................... 284
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage
Detection Circuits............................................................................ 285
17.1 Features............................................................................................................................. 286
17.2 Register Descriptions........................................................................................................ 288
17.2.1 Low-Voltage-Detection Control Register (LVDCR)........................................ 288
17.2.2 Low-Voltage-Detection Status Register (LVDSR)........................................... 290
17.3 Operations......................................................................................................................... 291
17.3.1 Power-On Reset Circuit .................................................................................... 291
17.3.2 Low-Voltage Detection Circuit......................................................................... 292
Section 18 Power Supply Circuit ...................................................................... 299
18.1 When Using Internal Power Supply Step-Down Circuit .................................................. 299
18.2 When Not Using Internal Power Supply Step-Down Circuit ........................................... 300
Section 19 List of Registers............................................................................... 301
19.1 Register Addresses (Address Order)................................................................................. 302
19.2 Register Bits ..................................................................................................................... 306
19.3 Register States in Each Operating Mode .......................................................................... 309
Section 20 Electrical Characteristics ................................................................. 313
20.1 Absolute Maximum Ratings ............................................................................................. 313
20.2 Electrical Characteristics (F-ZTAT
Rev. 3.00 Sep. 14, 2006 Page xvi of xxviii
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