Port States In Each Operating State; Figure B.16 Port C Block Diagram (Pc0) - Renesas H8 Series Hardware Manual

Appendix
Internal data bus
CPG
PMRC0
EXTALI
[Legend]
PDR: Portdata register
PCR: Portcontrol register
B.2

Port States in Each Operating State

Port Reset
P17, P14 High impedance
P22 to P20 High impedance
P57 to P55 High impedance
P76 to P74 High impedance
P84 to P80 High impedance
PB3 to PB0 High impedance
PC1, PC0 High impedance
Note: * High level output when the pull-up MOS is in on state.
Rev. 3.00 Sep. 14, 2006 Page 394 of 408
REJ09B0105-0300
PDR
PCR

Figure B.16 Port C Block Diagram (PC0)

Active
Functioning
Functioning
Functioning
Functioning
Functioning
High
impedance
Functioning
SBY
Sleep Subsleep
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
High Retained
impedance
Retained Retained
Standby
High impedance*
High impedance
High impedance*
High impedance
High impedance
High impedance
High impedance