Section 13 Watchdog Timer; Features; Figure 13.1 Block Diagram Of Watchdog Timer - Renesas H8 Series Hardware Manual

The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the watchdog timer is shown in figure 13.1.
WDT dedicated
internal oscillator
φ
[Legend]
TCSRWD: Timer control/status register WD
TCWD:
PSS:
TMWD:
13.1

Features

• Selectable from nine counter input clocks.
Eight clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192) or the
WDT dedicated internal oscillator can be selected as the timer-counter clock. When the WDT
dedicated internal oscillator is selected, it can operate as the watchdog timer in any operating
mode.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
• The watchdog timer is enabled in the initial state.
It starts operating after the reset state is canceled.
WDT0110A_000020030300

Section 13 Watchdog Timer

CLK
PSS
Timer counter WD
Prescaler S
Timer mode register WD

Figure 13.1 Block Diagram of Watchdog Timer

Section 13 Watchdog Timer
TCSRWD
TCWD
TMWD
Internal reset
signal
Rev. 3.00 Sep. 14, 2006 Page 191 of 408
REJ09B0105-0300