Renesas H8 Series Hardware Manual page 73

As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.
However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy
of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work
area, then write this data to PDR5.
[Prior to executing BSET]
MOV.B #80,
MOV.B R0L,
MOV.B R0L,
P57
Input/output Input
Pin state Low
level
PCR5 0
PDR5 1
RAM0 1
[BSET instruction executed]
BSET #0,
[After executing BSET]
MOV.B @RAM0, R0L
MOV.B R0L,
P57
Input/output Input
Pin state Low
level
PCR5 0
PDR5 1
RAM0 1
R0L
The PDR5 value (H'80) is written to a work area in
@RAM0
memory (RAM0) as well as to PDR5.
@PDR5
P56 P55
Input Output
High Low
level level
0 1
0 0
0 0
@RAM0
The BSET instruction is executed designating the PDR5
work area (RAM0).
The work area (RAM0) value is written to PDR5.
@PDR5
P56 P55
Input Output
High Low
level level
0 1
0 0
0 0
P54 P53 P52
Output Output Output
Low Low Low
level level level
1 1 1
0 0 0
0 0 0
P54 P53 P52
Output Output Output
Low Low Low
level level level
1 1 1
0 0 0
0 0 0
Rev. 3.00 Sep. 14, 2006 Page 43 of 408
Section 2 CPU
P51 P50
Output Output
Low Low
level level
1 1
0 0
0 0
P51 P50
Output Output
Low High
level level
1 1
0 1
0 1
REJ09B0105-0300