Serial Status Register (Ssr) - Renesas H8 Series Hardware Manual

Section 14 Serial Communication Interface 3 (SCI3)
14.3.7

Serial Status Register (SSR)

SSR is a register containing status flags of SCI3 and multiprocessor bits for transfer. 1 cannot be
written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Bit Bit Name
7 TDRE
6 RDRF
5 OER
4 FER
Rev. 3.00 Sep. 14, 2006 Page 204 of 408
REJ09B0105-0300
Initial
Value R/W Description
1 R/W Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
0 R/W Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
0 R/W Overrun Error
[Setting condition]
•
[Clearing condition]
•
0 R/W Framing Error
[Setting condition]
•
[Clearing condition]
•
When the TE bit in SCR3 is 0
When data is transferred from TDR to TSR
When 0 is written to TDRE after reading TDRE = 1
When the transmit data is written to TDR
When serial reception ends normally and receive data
is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF = 1
When data is read from RDR
When an overrun error occurs in reception
When 0 is written to OER after reading OER = 1
When a framing error occurs in reception
When 0 is written to FER after reading FER = 1