Renesas H8 Series Hardware Manual page 17

14.6.1 Multiprocessor Serial Data Transmission ......................................................... 229
14.6.2 Multiprocessor Serial Data Reception .............................................................. 231
14.7 Interrupts........................................................................................................................... 235
14.8 Usage Notes ...................................................................................................................... 236
14.8.1 Break Detection and Processing ....................................................................... 236
14.8.2 Mark State and Break Sending.......................................................................... 236
14.8.3 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only).................................................................. 236
14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode ................................................................................................................. 237
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Section 15 I C Bus Interface 2 (IIC2) ................................................................239
15.1 Features............................................................................................................................. 239
15.2 Input/Output Pins.............................................................................................................. 241
15.3 Register Descriptions........................................................................................................ 242
2
15.3.1 I C Bus Control Register 1 (ICCR1)................................................................. 242
2
15.3.2 I C Bus Control Register 2 (ICCR2)................................................................. 245
2
15.3.3 I C Bus Mode Register (ICMR)........................................................................ 246
2
15.3.4 I C Bus Interrupt Enable Register (ICIER) ....................................................... 248
2
15.3.5 I C Bus Status Register (ICSR)......................................................................... 250
15.3.6 Slave Address Register (SAR).......................................................................... 252
2
15.3.7 I C Bus Transmit Data Register (ICDRT)......................................................... 253
2
15.3.8 I C Bus Receive Data Register (ICDRR).......................................................... 253
2
15.3.9 I C Bus Shift Register (ICDRS)........................................................................ 253
15.4 Operation .......................................................................................................................... 254
2
15.4.1 I C Bus Format.................................................................................................. 254
15.4.2 Master Transmit Operation ............................................................................... 255
15.4.3 Master Receive Operation................................................................................. 257
15.4.4 Slave Transmit Operation ................................................................................. 259
15.4.5 Slave Receive Operation................................................................................... 261
15.4.6 Clocked Synchronous Serial Format................................................................. 263
15.4.7 Noise Canceler.................................................................................................. 265
15.4.8 Example of Use................................................................................................. 266
15.5 Interrupts........................................................................................................................... 270
15.6 Bit Synchronous Circuit.................................................................................................... 271
15.7 Usage Notes ...................................................................................................................... 272
15.7.1 Issue (Retransmission) of Start/Stop Conditions .............................................. 272
15.7.2 WAIT Setting in I
2
C Bus Mode Register (ICMR) ............................................ 272
Rev. 3.00 Sep. 14, 2006 Page xv of xxviii