Timer Control Register V1 (Tcrv1) - Renesas H8 Series Hardware Manual

Bit Bit Name
1 OS1
0 OS0
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level
for compare match A. The two output levels can be controlled independently. After a reset, the
timer output is 0 until the first compare match.
11.3.5

Timer Control Register V1 (TCRV1)

TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to
TCNTV.
Bit Bit Name

7 to 5
4 TVEG1
3 TVEG0
2 TRGE
Initial
Value R/W Description
0 R/W Output Select 1 and 0
0 R/W These bits select an output method for the TMOV pin by
the compare match of TCORA and TCNTV.
00: No change
01: 0 output
10: 1 output
11: Output toggles
Initial
Value R/W Description

All 1 Reserved
These bits are always read as 1.
0 R/W TRGV Input Edge Select
0 R/W These bits select the TRGV input edge.
00: TRGV trigger input is prohibited
01: Rising edge is selected
10: Falling edge is selected
11: Rising and falling edges are both selected
0 R/W TCNT starts counting up by the input of the edge which is
selected by TVEG1 and TVEG0.
0: Disables starting counting-up TCNTV by the input of
1: Enables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
Rev. 3.00 Sep. 14, 2006 Page 151 of 408
Section 11 Timer V
REJ09B0105-0300