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HD64F36902G
Renesas HD64F36902G Manuals
Manuals and User Guides for Renesas HD64F36902G. We have
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Renesas HD64F36902G manuals available for free PDF download: Hardware Manual, User Manual
Renesas HD64F36902G Hardware Manual (442 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 2.49 MB
Table of Contents
Table of Contents
11
Section 1 Overview
31
Features
31
Section 1 Overview
32
Figure 1.1 Internal Block Diagram of H8/36912 Group
33
Internal Block Diagram
33
Figure 1.2 Internal Block Diagram of H8/36902 Group
34
Pin Arrangement
35
Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A)
35
Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A)
36
Figure 1.5 Pin Arrangement of H8/36912 Group (FP-32D, 32P4B)
37
Figure 1.6 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B)
38
Table 1.1 Pin Functions
39
Pin Functions
39
Section 2 CPU
41
Address Space and Memory Map
42
Figure 2.1 Memory Map (1)
42
Section 2 CPU
42
Figure 2.1 Memory Map (2)
43
Register Configuration
44
Figure 2.2 CPU Registers
44
Figure 2.3 Usage of General Registers
45
General Registers
45
Condition-Code Register (CCR)
46
Figure 2.4 Relationship between Stack Pointer and Stack Area
46
Program Counter (PC)
46
Data Formats
48
General Register Data Formats
48
Figure 2.5 General Register Data Formats (1)
48
Figure 2.5 General Register Data Formats (2)
49
Memory Data Formats
50
Figure 2.6 Memory Data Formats
50
Instruction Set
51
Table of Instructions Classified by Function
51
Table 2.1 Operation Notation
51
Table 2.2 Data Transfer Instructions
52
Table 2.3 Arithmetic Operations Instructions (1)
53
Table 2.3 Arithmetic Operations Instructions (2)
54
Table 2.4 Logic Operations Instructions
55
Table 2.5 Shift Instructions
55
Table 2.6 Bit Manipulation Instructions (1)
56
Table 2.6 Bit Manipulation Instructions (2)
57
Table 2.7 Branch Instructions
58
Table 2.8 System Control Instructions
59
Basic Instruction Formats
60
Table 2.9 Block Data Transfer Instructions
60
Figure 2.7 Instruction Formats
61
Addressing Modes and Effective Address Calculation
62
Addressing Modes
62
Table 2.10 Addressing Modes
62
Table 2.11 Absolute Address Access Ranges
64
Effective Address Calculation
65
Figure 2.8 Branch Address Specification in Memory Indirect Mode
65
Table 2.12 Effective Address Calculation (1)
65
Table 2.12 Effective Address Calculation (2)
66
Basic Bus Cycle
67
Access to On-Chip Memory (RAM, ROM)
67
Figure 2.9 On-Chip Memory Access Cycle
67
On-Chip Peripheral Modules
68
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
68
Figure 2.11 CPU Operation States
69
CPU States
69
Usage Notes
70
Notes on Data Access to Empty Areas
70
EEPMOV Instruction
70
Bit Manipulation Instruction
70
Figure 2.12 State Transitions
70
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to same
71
Table 3.1 Exception Sources and Vector Address
77
Section 3 Exception Handling
77
Exception Sources and Vector Address
77
Register Descriptions
79
Interrupt Edge Select Register 1 (IEGR1)
79
Interrupt Edge Select Register 2 (IEGR2)
80
Interrupt Enable Register 1 (IENR1)
80
Interrupt Enable Register 2 (IENR2)
81
Interrupt Flag Register 1 (IRR1)
82
Interrupt Flag Register 2 (IRR2)
83
Wakeup Interrupt Flag Register (IWPR)
83
Reset Exception Handling
84
Interrupt Exception Handling
85
External Interrupts
85
Internal Interrupts
86
Figure 3.1 Reset Sequence
86
Interrupt Handling Sequence
87
Figure 3.2 Stack Status after Exception Handling
88
Interrupt Response Time
89
Table 3.2 Interrupt Wait States
89
Figure 3.3 Interrupt Sequence
90
Usage Notes
91
Interrupts after Reset
91
Notes on Stack Area Use
91
Notes on Rewriting Port Mode Registers
91
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
91
Section 4 Address Break
93
Figure 4.1 Block Diagram of Address Break
93
Register Descriptions
94
Address Break Control Register (ABRKCR)
94
Address Break Status Register (ABRKSR)
96
Break Address Registers (BARH, BARL)
96
Break Data Registers (BDRH, BDRL)
96
Operation
97
Figure 4.2 Address Break Interrupt Operation Example (1)
97
Figure 4.2 Address Break Interrupt Operation Example (2)
98
Figure 5.1 Block Diagram of Clock Pulse Generators
99
Section 5 Clock Pulse Generators
99
Features
100
Register Descriptions
101
RC Control Register (RCCR)
101
RC Trimming Data Protect Register (RCTRMDPR)
102
RC Trimming Data Register (RCTRMDR)
103
Clock Control/Status Register (CKCSR)
104
System Clock Select Operation
105
Figure 5.2 State Transition of System Clock
105
Clock Control Operation
106
Figure 5.3 Flowchart of Clock Switching On-Chip Oscillator Clock to External Clock (1)
106
Figure 5.4 Flowchart of Clock Switching External Clock to On-Chip Oscillator Clock (2)
107
Clock Change Timing
108
Figure 5.5 Timing Chart of Switching On-Chip Oscillator Clock to External Clock
108
Figure 5.6 Timing Chart to Switch External Clock to On-Chip Oscillator Clock
109
Figure 5.7 Example of Trimming Flow for On-Chip Oscillator Frequency
110
Trimming of On-Chip Oscillator Frequency
110
Figure 5.8 Timing Chart of Trimming of On-Chip Oscillator Frequency
111
External Oscillators
112
Connecting Crystal Resonator
112
Figure 5.9 Example of Connection to Crystal Resonator
112
Figure 5.10 Equivalent Circuit of Crystal Resonator
112
Table 5.1 Crystal Resonator Parameters
112
Connecting Ceramic Resonator
113
External Clock Input Method
113
Prescaler
113
Prescaler S
113
Figure 5.11 Example of Connection to Ceramic Resonator
113
Figure 5.12 Example of External Clock Input
113
Usage Notes
114
Note on Resonators
114
Notes on Board Design
114
Figure 5.13 Example of Incorrect Board Design
114
Section 6 Power-Down Modes
115
Register Descriptions
115
System Control Register 1 (SYSCR1)
116
Table 6.1 Operating Frequency and Wait Time
117
System Control Register 2 (SYSCR2)
118
Module Standby Control Register 1 (MSTCR1)
119
Module Standby Control Register 2 (MSTCR2)
120
Mode Transitions and States of LSI
121
Figure 6.1 Mode Transition Diagram
121
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling
122
Table 6.3 Internal State in each Operating Mode
122
Sleep Mode
123
Standby Mode
123
Subsleep Mode
124
Operating Frequency in Active Mode
124
Direct Transition
124
Module Standby Function
125
Section 7 ROM
127
Block Configuration
127
Figure 7.1 Flash Memory Block Configuration
128
Register Descriptions
129
Flash Memory Control Register 1 (FLMCR1)
129
Flash Memory Control Register 2 (FLMCR2)
130
Erase Block Register 1 (EBR1)
131
Flash Memory Enable Register (FENR)
131
On-Board Programming Modes
132
Boot Mode
132
Table 7.1 Setting Programming Modes
132
Table 7.2 Boot Mode Operation
134
Table 7.3 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is Possible
135
Programming/Erasing in User Program Mode
136
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
136
Flash Memory Programming/Erasing
137
Program/Program-Verify
137
Figure 7.3 Program/Program-Verify Flowchart
138
Erase/Erase-Verify
139
Table 7.4 Reprogram Data Computation Table
139
Table 7.5 Additional-Program Data Computation Table
139
Table 7.6 Programming Time
139
Interrupt Handling When Programming/Erasing Flash Memory
140
Figure 7.4 Erase/Erase-Verify Flowchart
141
Program/Erase Protection
142
Hardware Protection
142
Software Protection
142
Error Protection
142
Section 8 RAM
145
Section 9 I/O Ports
147
Port 1
147
Figure 9.1 Port 1 Pin Configuration
147
Port Mode Register 1 (PMR1)
148
Port Control Register 1 (PCR1)
149
Port Data Register 1 (PDR1)
149
Pin Functions
150
Port Pull-Up Control Register 1 (PUCR1)
150
Port 2
151
Figure 9.2 Port 2 Pin Configuration
151
Port Control Register 2 (PCR2)
152
Port Data Register 2 (PDR2)
152
Pin Functions
153
Port 5
154
Figure 9.3 Port 5 Pin Configuration
154
Port Control Register 5 (PCR5)
155
Port Mode Register 5 (PMR5)
155
Port Data Register 5 (PDR5)
156
Port Pull-Up Control Register 5 (PUCR5)
156
Pin Functions
157
Port 7
158
Port Control Register 7 (PCR7)
158
Figure 9.4 Port 7 Pin Configuration
158
Port Data Register 7 (PDR7)
159
Pin Functions
159
Port 8
160
Figure 9.5 Port 8 Pin Configuration
160
Port Control Register 8 (PCR8)
161
Port Data Register 8 (PDR8)
161
Pin Functions
162
Port B
164
Port Data Register B (PDRB)
164
Figure 9.6 Port B Pin Configuration
164
Pin Functions
165
Port C
166
Figure 9.7 Port C Pin Configuration
166
Port Control Register C (PCRC)
167
Port Data Register C (PDRC)
167
Pin Functions
168
Figure 10.1 Block Diagram of Timer B1
169
Section 10 Timer B1
169
Features
169
Register Descriptions
170
Timer Mode Register B1 (TMB1)
170
Timer Counter B1 (TCB1)
171
Timer Load Register B1 (TLB1)
171
Operation
172
Interval Timer Operation
172
Auto-Reload Timer Operation
172
Table 10.1 Timer B1 Operating Modes
173
Timer B1 Operating Modes
173
Section 11 Timer V
175
Features
175
Input/Output Pins
177
Register Descriptions
177
Timer Counter V (TCNTV)
177
Table 11.1 Pin Configuration
177
Time Constant Registers a and B (TCORA, TCORB)
178
Timer Control Register V0 (TCRV0)
178
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions
179
Timer Control/Status Register V (TCSRV)
180
Timer Control Register V1 (TCRV1)
181
Operation
182
Timer V Operation
182
Figure 11.2 Increment Timing with Internal Clock
183
Figure 11.3 Increment Timing with External Clock
183
Figure 11.4 OVF Set Timing
183
Figure 11.5 CMFA and CMFB Set Timing
184
Figure 11.6 TMOV Output Timing
184
Figure 11.7 Clear Timing by Compare Match
184
Timer V Application Examples
185
Pulse Output with Arbitrary Duty Cycle
185
Figure 11.8 Clear Timing by TMRIV Input
185
Figure 11.9 Pulse Output Example
185
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
186
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input
186
Figure 11.11 Contention between TCNTV Write and Clear
187
Usage Notes
187
Figure 11.12 Contention between TCORA Write and Compare Match
188
Figure 11.13 Internal Clock Switching and TCNTV Operation
188
Section 12 Timer W
189
Features
189
Table 12.1 Timer W Functions
190
Figure 12.1 Timer W Block Diagram
191
Input/Output Pins
192
Register Descriptions
192
Table 12.2 Pin Configuration
192
Timer Mode Register W (TMRW)
193
Timer Control Register W (TCRW)
194
Timer Interrupt Enable Register W (TIERW)
195
Timer Status Register W (TSRW)
196
Timer I/O Control Register 0 (TIOR0)
198
Timer I/O Control Register 1 (TIOR1)
199
General Registers a to D (GRA to GRD)
201
Timer Counter (TCNT)
201
Operation
202
Normal Operation
202
Figure 12.2 Free-Running Counter Operation
202
Figure 12.3 Periodic Counter Operation
203
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)
203
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1)
204
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1)
204
Figure 12.7 Input Capture Operating Example
205
PWM Operation
206
Figure 12.8 Buffer Operation Example (Input Capture)
206
Figure 12.9 PWM Mode Example (1)
207
Figure 12.10 PWM Mode Example (2)
207
Figure 12.11 Buffer Operation Example (Output Compare)
208
Figure 12.12 PWM Mode Example (TOB, TOC, and TOD = 0: Initial Output Values Are Set to 0)
209
Figure 12.13 PWM Mode Example (TOB, TOC, and TOD = 1: Initial Output Values Are Set to 1)
210
Operation Timing
211
TCNT Count Timing
211
Figure 12.14 Count Timing for Internal Clock Source
211
Figure 12.15 Count Timing for External Clock Source
211
Output Compare Output Timing
212
Figure 12.16 Output Compare Output Timing
212
Input Capture Timing
213
Timing of Counter Clearing by Compare Match
213
Figure 12.17 Input Capture Input Signal Timing
213
Figure 12.18 Timing of Counter Clearing by Compare Match
213
Buffer Operation Timing
214
Figure 12.19 Buffer Operation Timing (Compare Match)
214
Figure 12.20 Buffer Operation Timing (Input Capture)
214
Timing of IMFA to IMFD Flag Setting at Compare Match
215
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match
215
Timing of IMFA to IMFD Setting at Input Capture
216
Timing of Status Flag Clearing
216
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture
216
Figure 12.23 Timing of Status Flag Clearing by CPU
216
Usage Notes
217
Figure 12.24 Contention between TCNT Write and Clear
218
Figure 12.25 Internal Clock Switching and TCNT Operation
218
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the same Timing
219
Figure 13.1 Block Diagram of Watchdog Timer
221
Section 13 Watchdog Timer
221
Features
221
Register Descriptions
222
Timer Control/Status Register WD (TCSRWD)
222
Timer Counter WD (TCWD)
224
Timer Mode Register WD (TMWD)
224
Figure 13.2 Watchdog Timer Operation Example
225
Operation
225
Section 14 Serial Communication Interface 3 (SCI3)
227
Features
227
Figure 14.1 Block Diagram of SCI3
228
Input/Output Pins
229
Register Descriptions
229
Table 14.1 Pin Configuration
229
Receive Data Register (RDR)
230
Receive Shift Register (RSR)
230
Transmit Data Register (TDR)
230
Transmit Shift Register (TSR)
230
Serial Mode Register (SMR)
231
Serial Control Register 3 (SCR3)
232
Serial Status Register (SSR)
234
Bit Rate Register (BRR)
236
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)
237
Table 14.3 Maximum Bit Rate for each Frequency (Asynchronous Mode)
239
Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
240
Figure 14.2 Block Diagram of Noise Filter Circuit
241
Sampling Mode Register (SPMR)
241
Operation in Asynchronous Mode
242
Clock
242
Figure 14.3 Data Format in Asynchronous Communication
242
Figure 14.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
242
SCI3 Initialization
243
Figure 14.5 Sample SCI3 Initialization Flowchart
243
Data Transmission
244
Figure 14.6 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
244
Figure 14.7 Sample Serial Transmission Data Flowchart (Asynchronous Mode)
245
Serial Data Reception
246
Figure 14.8 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
246
Table 14.5 SSR Status Flags and Receive Data Handling
247
Figure 14.9 Sample Serial Reception Data Flowchart (Asynchronous Mode)
248
Operation in Clocked Synchronous Mode
249
Clock
249
Figure 14.10 Data Format in Clocked Synchronous Communication
249
SCI3 Initialization
250
Serial Data Transmission
250
Figure 14.11 Example of SCI3 Transmission in Clocked Synchronous Mode
251
Figure 14.12 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
252
Serial Data Reception (Clocked Synchronous Mode)
253
Figure 14.13 Example of SCI3 Reception in Clocked Synchronous Mode
253
Figure 14.14 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
254
Simultaneous Serial Data Transmission and Reception
255
Figure 14.15 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)
256
Multiprocessor Communication Function
257
Figure 14.16 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
258
Multiprocessor Serial Data Transmission
259
Figure 14.17 Sample Multiprocessor Serial Transmission Flowchart
260
Multiprocessor Serial Data Reception
261
Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1)
262
Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2)
263
Figure 14.19 Example of SCI3 Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
264
Interrupts
265
Table 14.6 SCI3 Interrupt Requests
265
Usage Notes
266
Break Detection and Processing
266
Mark State and Break Sending
266
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
266
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
267
Figure 14.20 Receive Data Sampling Timing in Asynchronous Mode
267
Section 15 I C Bus Interface 2 (IIC2)
269
Features
269
Figure 15.1 Block Diagram of I
270
Input/Output Pins
271
Table 15.1 Pin Configuration
271
Figure 15.2 External Circuit Connections of I/O Pins
271
Register Descriptions
272
C Bus Control Register 1 (ICCR1)
272
Table 15.2 Transfer Rate
274
C Bus Control Register 2 (ICCR2)
275
C Bus Mode Register (ICMR)
276
C Bus Interrupt Enable Register (ICIER)
278
C Bus Status Register (ICSR)
280
Slave Address Register (SAR)
282
C Bus Transmit Data Register (ICDRT)
283
C Bus Receive Data Register (ICDRR)
283
C Bus Shift Register (ICDRS)
283
Operation
284
C Bus Format
284
Figure 15.3 I 2 C Bus Formats
284
Figure 15.4 I 2 C Bus Timing
284
Master Transmit Operation
285
Figure 15.5 Master Transmit Mode Operation Timing (1)
286
Figure 15.6 Master Transmit Mode Operation Timing (2)
286
Master Receive Operation
287
Figure 15.7 Master Receive Mode Operation Timing (1)
288
Slave Transmit Operation
289
Figure 15.8 Master Receive Mode Operation Timing (2)
289
Figure 15.9 Slave Transmit Mode Operation Timing (1)
290
Slave Receive Operation
291
Figure 15.10 Slave Transmit Mode Operation Timing (2)
291
Figure 15.11 Slave Receive Mode Operation Timing (1)
292
Figure 15.12 Slave Receive Mode Operation Timing (2)
292
Clocked Synchronous Serial Format
293
Figure 15.13 Clocked Synchronous Serial Transfer Format
293
Figure 15.14 Transmit Mode Operation Timing
294
Noise Canceler
295
Figure 15.15 Receive Mode Operation Timing
295
Figure 15.16 Block Diagram of Noise Canceler
295
Example of Use
296
Figure 15.17 Sample Flowchart for Master Transmit Mode
296
Figure 15.18 Sample Flowchart for Master Receive Mode
297
Figure 15.19 Sample Flowchart for Slave Transmit Mode
298
Figure 15.20 Sample Flowchart for Slave Receive Mode
299
Table 15.3 Interrupt Requests
300
Interrupts
300
Figure 15.21 Timing of Bit Synchronous Circuit
301
Table 15.4 Time for Monitoring SCL
301
Bit Synchronous Circuit
301
Usage Notes
302
Issue (Retransmission) of Start/Stop Conditions
302
WAIT Setting in I C Bus Mode Register (ICMR)
302
Section 16 A/D Converter
303
Features
303
Figure 16.1 Block Diagram of A/D Converter
304
Input/Output Pins
305
Register Description
305
A/D Data Registers a to D (ADDRA to ADDRD)
305
Table 16.1 Pin Configuration
305
A/D Control/Status Register (ADCSR)
306
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
306
A/D Control Register (ADCR)
308
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Renesas HD64F36902G User Manual (408 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 3.85 MB
Table of Contents
General Precautions on Handling of Product
4
Preface
6
Table of Contents
9
Appendix
24
Section 1 Overview
29
Features
29
Internal Block Diagram
31
Figure 1.1 Internal Block Diagram of H8/36912 Group
31
Figure 1.2 Internal Block Diagram of H8/36902 Group
32
Section 2 CPU
32
Section 2 CPU
31
Figure 1.3 Pin Arrangement of H8/36912 Group (LQFP-32)
33
Pin Arrangement
33
Figure 1.4 Pin Arrangement of H8/36902 Group (LQFP-32)
34
Figure 1.5 Pin Arrangement of H8/36912 Group (SOP-32)
35
Figure 1.6 Pin Arrangement of H8/36902 Group (SOP-32)
36
Table 1.1 Pin Functions
37
Pin Functions
37
Manual
38
Section 2 CPU
39
Address Space and Memory Map
40
Figure 2.1 Memory Map (1)
40
Figure 2.1 Memory Map (2)
41
Register Configuration
42
Figure 2.2 CPU Registers
42
Figure 2.3 Usage of General Registers
43
General Registers
43
Condition-Code Register (CCR)
44
Figure 2.4 Relationship between Stack Pointer and Stack Area
44
Program Counter (PC)
44
Data Formats
46
General Register Data Formats
46
Figure 2.5 General Register Data Formats (1)
46
Figure 2.5 General Register Data Formats (2)
47
Memory Data Formats
48
Figure 2.6 Memory Data Formats
48
Instruction Set
49
Table of Instructions Classified by Function
49
Table 2.1 Operation Notation
49
Table 2.2 Data Transfer Instructions
50
Table 2.3 Arithmetic Operations Instructions (1)
51
Table 2.3 Arithmetic Operations Instructions (2)
52
Table 2.4 Logic Operations Instructions
52
Table 2.5 Shift Instructions
53
Table 2.6 Bit Manipulation Instructions (1)
55
Table 2.6 Bit Manipulation Instructions (2)
55
Table 2.7 Branch Instructions
56
Table 2.8 System Control Instructions
57
Table 2.9 Block Data Transfer Instructions
57
Basic Instruction Formats
58
Figure 2.7 Instruction Formats
58
Addressing Modes and Effective Address Calculation
59
Addressing Modes
59
Table 2.10 Addressing Modes
59
Table 2.11 Absolute Address Access Ranges
60
Figure 2.8 Branch Address Specification in Memory Indirect Mode
61
Effective Address Calculation
62
Table 2.12 Effective Address Calculation (1)
62
Table 2.12 Effective Address Calculation (2)
63
Basic Bus Cycle
64
Access to On-Chip Memory (RAM, ROM)
64
Figure 2.9 On-Chip Memory Access Cycle
64
On-Chip Peripheral Modules
65
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
65
Figure 2.11 CPU Operation States
66
Figure 2.12 State Transitions
66
CPU States
66
Usage Notes
67
Notes on Data Access to Empty Areas
67
EEPMOV Instruction
67
Bit Manipulation Instruction
67
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to same
68
Section 3 Exception Handling
73
Exception Sources and Vector Address
73
Register Descriptions
75
Interrupt Edge Select Register 1 (IEGR1)
75
Interrupt Edge Select Register 2 (IEGR2)
76
Interrupt Enable Register 1 (IENR1)
76
Interrupt Enable Register 2 (IENR2)
77
Interrupt Flag Register 1 (IRR1)
78
Interrupt Flag Register 2 (IRR2)
79
Wakeup Interrupt Flag Register (IWPR)
79
Reset Exception Handling
80
Interrupt Exception Handling
81
External Interrupts
81
Internal Interrupts
82
Interrupt Handling Sequence
82
Figure 3.1 Reset Sequence
82
Figure 3.2 Stack Status after Exception Handling
83
Interrupt Response Time
84
Table 3.2 Interrupt Wait States
84
Figure 3.3 Interrupt Sequence
85
Usage Notes
86
Interrupts after Reset
86
Notes on Stack Area Use
86
Notes on Rewriting Port Mode Registers
86
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
86
Section 4 Address Break
87
Register Descriptions
87
Figure 4.1 Block Diagram of Address Break
87
Address Break Control Register (ABRKCR)
88
Address Break Status Register (ABRKSR)
89
Table 4.1 Access and Data Bus Used
89
Break Address Registers (BARH, BARL)
90
Break Data Registers (BDRH, BDRL)
90
Operation
91
Figure 4.2 Address Break Interrupt Operation Example (1)
91
Figure 4.2 Address Break Interrupt Operation Example (2)
92
Section 5 Clock Pulse Generators
93
Figure 5.1 Block Diagram of Clock Pulse Generators
93
Features
94
Register Descriptions
95
RC Control Register (RCCR)
95
RC Trimming Data Protect Register (RCTRMDPR)
96
RC Trimming Data Register (RCTRMDR)
97
Clock Control/Status Register (CKCSR)
97
System Clock Select Operation
99
Figure 5.2 State Transition of System Clock
99
Clock Control Operation
100
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled
100
Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1) (from Internal RC Clock to External Clock)
101
Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2) (from External Clock to Internal RC Clock)
102
Clock Change Timing
103
Figure 5.6 Timing Chart of Switching Internal RC Clock to External Clock
103
Figure 5.7 Timing Chart to Switch External Clock to Internal RC Clock
104
Figure 5.8 External Oscillation Backup Timing
105
Figure 5.9 Example of Trimming Flow for Internal RC Oscillator Frequency
106
Trimming of Internal RC Oscillator Frequency
106
Figure 5.10 Timing Chart of Trimming of Internal RC Oscillator Frequency
107
External Oscillators
108
Connecting Crystal Resonator
108
Figure 5.11 Example of Connection to Crystal Resonator
108
Figure 5.12 Equivalent Circuit of Crystal Resonator
108
Table 5.1 Crystal Resonator Parameters
108
Connecting Ceramic Resonator
109
External Clock Input Method
109
Prescaler
109
Prescaler S
109
Figure 5.13 Example of Connection to Ceramic Resonator
109
Figure 5.14 Example of External Clock Input
109
Usage Notes
110
Note on Resonators
110
Notes on Board Design
110
Figure 5.15 Example of Incorrect Board Design
110
Section 6 Power-Down Modes
111
Register Descriptions
112
System Control Register 1 (SYSCR1)
112
System Control Register 2 (SYSCR2)
114
Module Standby Control Register 1 (MSTCR1)
115
Module Standby Control Register 2 (MSTCR2)
116
Mode Transitions and States of LSI
117
Figure 6.1 Mode Transition Diagram
117
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling
117
Sleep Mode
118
Table 6.3 Internal State in each Operating Mode
118
Standby Mode
119
Subsleep Mode
119
Operating Frequency in Active Mode
120
Direct Transition
120
Module Standby Function
120
Section 7 ROM
121
Block Configuration
122
Figure 7.1 Flash Memory Block Configuration
123
Register Descriptions
124
Flash Memory Control Register 1 (FLMCR1)
124
Flash Memory Control Register 2 (FLMCR2)
125
Erase Block Register 1 (EBR1)
126
Flash Memory Enable Register (FENR)
126
On-Board Programming Modes
127
Boot Mode
127
Table 7.1 Setting Programming Modes
127
Table 7.2 Boot Mode Operation
129
Programming/Erasing in User Program Mode
130
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
130
Table 7.3 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is
130
Flash Memory Programming/Erasing
131
Program/Program-Verify
131
Figure 7.3 Program/Program-Verify Flowchart
132
Erase/Erase-Verify
133
Table 7.4 Reprogram Data Computation Table
133
Table 7.5 Additional-Program Data Computation Table
133
Table 7.6 Programming Time
133
Interrupt Handling When Programming/Erasing Flash Memory
134
Figure 7.4 Erase/Erase-Verify Flowchart
135
Program/Erase Protection
136
Hardware Protection
136
Software Protection
136
Error Protection
136
Section 8 RAM
137
Section 9 I/O Ports
139
Port 1
139
Figure 9.1 Port 1 Pin Configuration
139
Port Mode Register 1 (PMR1)
140
Port Control Register 1 (PCR1)
141
Port Data Register 1 (PDR1)
141
Pin Functions
142
Port Pull-Up Control Register 1 (PUCR1)
142
Port 2
143
Port Control Register 2 (PCR2)
143
Figure 9.2 Port 2 Pin Configuration
143
Port Data Register 2 (PDR2)
144
Pin Functions
144
Port 5
145
Figure 9.3 Port 5 Pin Configuration
145
Port Control Register 5 (PCR5)
146
Port Mode Register 5 (PMR5)
146
Port Data Register 5 (PDR5)
147
Port Pull-Up Control Register 5 (PUCR5)
147
Pin Functions
148
Port 7
149
Port Control Register 7 (PCR7)
149
Figure 9.4 Port 7 Pin Configuration
149
Port Data Register 7 (PDR7)
150
Pin Functions
150
Port 8
151
Figure 9.5 Port 8 Pin Configuration
151
Port Control Register 8 (PCR8)
152
Port Data Register 8 (PDR8)
152
Pin Functions
153
Port B
155
Port Data Register B (PDRB)
155
Figure 9.6 Port B Pin Configuration
155
Pin Functions
156
Port C
158
Figure 9.7 Port C Pin Configuration
158
Pin Functions
159
Port Control Register C (PCRC)
159
Port Data Register C (PDRC)
159
Figure 10.1 Block Diagram of Timer B1
161
Section 10 Timer B1
161
Features
161
Register Descriptions
162
Timer Mode Register B1 (TMB1)
162
Timer Counter B1 (TCB1)
163
Timer Load Register B1 (TLB1)
163
Table 10.1 Timer B1 Operating Modes
164
Operation
164
Interval Timer Operation
164
Auto-Reload Timer Operation
164
Timer B1 Operating Modes
164
Section 11 Timer V
165
Features
165
Table 11.1 Pin Configuration
166
Input/Output Pins
166
Register Descriptions
167
Timer Counter V (TCNTV)
167
Time Constant Registers a and B (TCORA, TCORB)
167
Timer Control Register V0 (TCRV0)
168
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions
169
Timer Control/Status Register V (TCSRV)
170
Timer Control Register V1 (TCRV1)
171
Operation
172
Timer V Operation
172
Figure 11.2 Increment Timing with Internal Clock
172
Figure 11.3 Increment Timing with External Clock
173
Figure 11.4 OVF Set Timing
173
Figure 11.5 CMFA and CMFB Set Timing
173
Figure 11.6 TMOV Output Timing
174
Figure 11.7 Clear Timing by Compare Match
174
Figure 11.8 Clear Timing by TMRIV Input
174
Timer V Application Examples
175
Pulse Output with Arbitrary Duty Cycle
175
Figure 11.9 Pulse Output Example
175
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
176
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input
176
Figure 11.11 Contention between TCNTV Write and Clear
177
Usage Notes
177
Figure 11.12 Contention between TCORA Write and Compare Match
178
Figure 11.13 Internal Clock Switching and TCNTV Operation
178
Section 12 Timer W
179
Features
179
Table 12.1 Timer W Functions
180
Figure 12.1 Timer W Block Diagram
181
Table 12.2 Pin Configuration
181
Input/Output Pins
181
Register Descriptions
182
Timer Mode Register W (TMRW)
183
Timer Control Register W (TCRW)
184
Timer Interrupt Enable Register W (TIERW)
185
Timer Status Register W (TSRW)
186
Timer I/O Control Register 0 (TIOR0)
188
Timer I/O Control Register 1 (TIOR1)
189
Timer Counter (TCNT)
191
General Registers a to D (GRA to GRD)
191
Operation
192
Normal Operation
192
Figure 12.2 Free-Running Counter Operation
192
Figure 12.3 Periodic Counter Operation
193
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)
193
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1)
194
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1)
194
Figure 12.7 Input Capture Operating Example
195
Figure 12.8 Buffer Operation Example (Input Capture)
195
PWM Operation
196
Figure 12.9 PWM Mode Example (1)
196
Figure 12.10 PWM Mode Example (2)
197
Figure 12.11 Buffer Operation Example (Output Compare)
197
Figure 12.12 PWM Mode Example
198
Figure 12.13 PWM Mode Example
199
Operation Timing
200
TCNT Count Timing
200
Figure 12.14 Count Timing for Internal Clock Source
200
Figure 12.15 Count Timing for External Clock Source
200
Output Compare Output Timing
201
Figure 12.16 Output Compare Output Timing
201
Input Capture Timing
202
Timing of Counter Clearing by Compare Match
202
Figure 12.17 Input Capture Input Signal Timing
202
Figure 12.18 Timing of Counter Clearing by Compare Match
202
Buffer Operation Timing
203
Figure 12.19 Buffer Operation Timing (Compare Match)
203
Figure 12.20 Buffer Operation Timing (Input Capture)
203
Timing of IMFA to IMFD Flag Setting at Compare Match
204
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match
204
Timing of IMFA to IMFD Setting at Input Capture
205
Timing of Status Flag Clearing
205
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture
205
Figure 12.23 Timing of Status Flag Clearing by CPU
205
Usage Notes
206
Figure 12.24 Contention between TCNT Write and Clear
207
Figure 12.25 Internal Clock Switching and TCNT Operation
207
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur
208
Figure 13.1 Block Diagram of Watchdog Timer
209
Section 13 Watchdog Timer
209
Features
209
Register Descriptions
210
Timer Control/Status Register WD (TCSRWD)
210
Timer Counter WD (TCWD)
212
Timer Mode Register WD (TMWD)
212
Figure 13.2 Watchdog Timer Operation Example
213
Operation
213
Section 14 Serial Communication Interface 3 (SCI3)
215
Features
215
Figure 14.1 Block Diagram of SCI3
216
Input/Output Pins
217
Register Descriptions
217
Table 14.1 Pin Configuration
217
Receive Data Register (RDR)
218
Receive Shift Register (RSR)
218
Transmit Data Register (TDR)
218
Transmit Shift Register (TSR)
218
Serial Mode Register (SMR)
219
Serial Control Register 3 (SCR3)
220
Serial Status Register (SSR)
222
Bit Rate Register (BRR)
224
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)
225
Table 14.3 Maximum Bit Rate for each Frequency (Asynchronous Mode)
227
Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
228
Figure 14.2 Block Diagram of Noise Filter Circuit
229
Sampling Mode Register (SPMR)
229
Operation in Asynchronous Mode
230
Clock
230
Figure 14.3 Data Format in Asynchronous Communication
230
Figure 14.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits)
230
SCI3 Initialization
231
Figure 14.5 Sample SCI3 Initialization Flowchart
231
Data Transmission
232
Figure 14.6 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
232
Figure 14.7 Sample Serial Transmission Data Flowchart (Asynchronous Mode)
233
Serial Data Reception
234
Figure 14.8 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
234
Figure 14.9 Sample Serial Reception Data Flowchart (Asynchronous Mode)
235
Table 14.5 SSR Status Flags and Receive Data Handling
235
Operation in Clocked Synchronous Mode
236
Clock
236
SCI3 Initialization
236
Figure 14.10 Data Format in Clocked Synchronous Communication
236
Serial Data Transmission
237
Figure 14.11 Example of SCI3 Transmission in Clocked Synchronous Mode
237
Figure 14.12 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
238
Serial Data Reception (Clocked Synchronous Mode)
239
Figure 14.13 Example of SCI3 Reception in Clocked Synchronous Mode
239
Figure 14.14 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
240
Simultaneous Serial Data Transmission and Reception
241
Figure 14.15 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)
242
Multiprocessor Communication Function
243
Figure 14.16 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
244
Figure 14.17 Sample Multiprocessor Serial Transmission Flowchart
245
Multiprocessor Serial Data Transmission
245
Multiprocessor Serial Data Reception
246
Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1)
247
Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2)
248
Figure 14.19 Example of SCI3 Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
249
Table 14.6 SCI3 Interrupt Requests
250
Interrupts
250
Usage Notes
251
Break Detection and Processing
251
Mark State and Break Sending
251
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
251
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
252
Figure 14.20 Receive Data Sampling Timing in Asynchronous Mode
252
Section 15 I C Bus Interface 2 (IIC2)
253
Features
253
Figure 15.1 Block Diagram of I
254
Input/Output Pins
255
Register Descriptions
255
Figure 15.2 External Circuit Connections of I/O Pins
255
Table 15.1 Pin Configuration
255
C Bus Control Register 1 (ICCR1)
256
C Bus Control Register 2 (ICCR2)
257
Table 15.2 Transfer Rate
257
C Bus Mode Register (ICMR)
259
C Bus Interrupt Enable Register (ICIER)
260
C Bus Status Register (ICSR)
262
Slave Address Register (SAR)
264
C Bus Receive Data Register (ICDRR)
265
C Bus Shift Register (ICDRS)
265
C Bus Transmit Data Register (ICDRT)
265
Operation
266
I 2 C Bus Format
266
Figure 15.3 I 2 C Bus Formats
266
Figure 15.4 I 2 C Bus Timing
266
Master Transmit Operation
267
Figure 15.5 Master Transmit Mode Operation Timing (1)
268
Figure 15.6 Master Transmit Mode Operation Timing (2)
268
Master Receive Operation
269
Figure 15.7 Master Receive Mode Operation Timing (1)
270
Figure 15.8 Master Receive Mode Operation Timing (2)
270
Slave Transmit Operation
271
Figure 15.9 Slave Transmit Mode Operation Timing (1)
271
Slave Receive Operation
272
Figure 15.10 Slave Transmit Mode Operation Timing (2)
272
Figure 15.11 Slave Receive Mode Operation Timing (1)
273
Figure 15.12 Slave Receive Mode Operation Timing (2)
273
Clocked Synchronous Serial Format
274
Figure 15.13 Clocked Synchronous Serial Transfer Format
274
Figure 15.14 Transmit Mode Operation Timing
275
Receive Operation
275
Noise Canceler
276
Figure 15.15 Receive Mode Operation Timing
276
Figure 15.16 Block Diagram of Noise Canceler
276
Example of Use
277
Figure 15.17 Sample Flowchart for Master Transmit Mode
277
Figure 15.18 Sample Flowchart for Master Receive Mode
278
Figure 15.19 Sample Flowchart for Slave Transmit Mode
279
Figure 15.20 Sample Flowchart for Slave Receive Mode
280
Table 15.3 Interrupt Requests
281
Interrupts
281
Figure 15.21 Timing of Bit Synchronous Circuit
282
Table 15.4 Time for Monitoring SCL
282
Bit Synchronous Circuit
282
Section 16 A/D Converter
283
Features
283
Figure 16.1 Block Diagram of A/D Converter
284
Input/Output Pins
285
Register Description
285
A/D Data Registers a to D (ADDRA to ADDRD)
285
Table 16.1 Pin Configuration
285
A/D Control/Status Register (ADCSR)
286
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
286
A/D Control Register (ADCR)
287
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