Figure 17.4 Operating Timing Of Lvdr Circuit - Renesas H8 Series Hardware Manual

V
CC
V
LVDRmin
LVDRES
PSS-reset
signal
OVF
Internal reset
signal
(2) Low Voltage Detection Interrupt (LVDI) Circuit
(When Internally Generated Voltage is used for Detection)
Figure 17.5 shows the timing of the operation of the LVDI circuit.
The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled. To
enable the LVDI, the LVDDF bit and LVDUF bit in LVDSR must be cleared to 0 and then the
LVDDE bit or LVDUE bit in LVDCR must be set to 1. After that, the output settings of ports
must be made.
To cancel the LVDI, follow the procedures written in section 17.3.2 (4), Operating Procedures for
Enabling/Disabling LVDR and LVDI Circuits.
To restart the LVDI circuit after standby mode, set the LVDE bit to 1, write 1 to VDDII (if
necessary), and wait for 50 µs (t
low-voltage detection power supply have settled. Then, clear the LVDDF and LVDUF bits to 0
and set the LVDDE or the LVDUE bit to 1. After that, the output settings of ports must be made.
When the power-supply voltage falls below Vint (D) (Typ. = 3.7 V) voltage, the LVDI circuit
clears the LVDINT signal to 0 and sets the LVDDF bit to 1. If the LVDDE bit is 1 at this time, an
IRQ0 interrupt request is generated. In this case, the necessary data must be saved in the external
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
PSS counter starts

Figure 17.4 Operating Timing of LVDR Circuit

) given by a software timer until the reference voltage and the
LVDON
131,072 cycles
Reset released
Rev. 3.00 Sep. 14, 2006 Page 293 of 408
Vreset
V
SS
REJ09B0105-0300