Figure 12.1 Timer W Block Diagram - Renesas H8 Series Hardware Manual

φ
Internal clock:
φ /2
φ /4
φ /8
External clock: FTCI
Comparator
[Legend]
TMRW: Timer mode register W (8 bits)
TCRW: Timer control register W (8 bits)
TIERW: Timer interrupt enable register W (8 bits)
TSRW: Timer status register W (8 bits)
TIOR: Timer I/O control register (8 bits)
TCNT: Timer counter (16 bits)
GRA: General register A (input capture/output compare register: 16 bits)
GRB: General register B (input capture/output compare register: 16 bits)
GRC: General register C (input capture/output compare register: 16 bits)
GRD: General register D (input capture/output compare register: 16 bits)
IRRTW: Timer W interrupt request

Figure 12.1 Timer W Block Diagram

Clock
selector
Control logic
Section 12 Timer W
Rev. 3.00 Sep. 14, 2006 Page 161 of 408
FTIOA
FTIOB
FTIOC
FTIOD
IRRTW
Internal
data bus
REJ09B0105-0300