Coeccerrlog - Channel 0 Ecc Error Log; Channel 0 Ecc Error Registers - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

6.1.6

COECCERRLOG - Channel 0 ECC Error Log

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is used to store the error status information in ECC enabled
configurations, along with the error syndrome and the rank/bank/row/column address
information of the address block of main memory of which an error (single bit or multi-
bit error) has occurred. Note that the address fields represent the address of the first
single or the first multiple bit error occurrence after the error flag bits in the ERRSTS
register have been cleared by software. A multiple bit error will overwrite a single bit
error. Once the error flag bits are set as a result of an error, this bit field is locked and
doesn't change as a result of a new error until the error flag is cleared by software.
Same is the case with error syndrome field, but the following priority needs to be
followed if more than one error occurs on one or more of the 4 QWs. MERR on QW0
MERR on QW1 MERR on QW2 MERR on QW3 CERR on QW0 CERR on QW1 CERR on
QW2 CERR on QW3.
Table 20. Channel 0 ECC Error Registers (Sheet 1 of 2)
Bit
63:48
47:32
31:29
28:27
26:24
23:16
15:2
1
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
78
Default
Access
Value
RO-P 0000h
RO-P 0000h
RO-P 000b
RO-P 00b
RO 000b
RO-P 00b
RO 0000h
RO-P 0b
Processor Configuration Registers
0/0/0/MCHBAR
280-287h
0000000000000000h
RO-P; RO
64 bits
RST/
PWR
Core Error Column Address (ERRCOL):
Row address of the address block of main
memory of which an error (single bit or multi-
bit error) has occurred.
Core Error Row Address (ERRROW):
Row address of the address block of main
memory of which an error (single bit or multi-
bit error) has occurred
Core Error Bank Address (ERRBANK):
Rank address of the address block of main
memory of which an error (single bit or multi-
bit error) has occurred
Error Rank Address (ERRRANK):
Core
Rank address of the address block of main
memory of which an error (single bit or multi-
bit error) has occurred.
Core Reserved
Core Error Syndrome (ERRSYND):
Syndrome that describes the set of bits
associated with the first failing quadword
Core Reserved
P
Core Multiple Bit Error Status (MERRSTS):
This bit is set when an uncorrectable multiple-
bit error occurs on a memory read data
transfer. When this bit is set, the address that
caused the error and the error syndrome are
also logged and they are locked until this bit is
cleared. This bit is cleared when it receives an
indication that the CPU has cleared the
corresponding bit in the ERRSTS register.
® ®
Celeron Processor P4505, U3405 Series
Description
August 2010
Document Number: 323178-003