Psmio - Xilinx ZCU104 User Manual

Table 3-4: DDR4 SODIMM Socket J1 Connections to FPGA PL Banks 64, 65, and 66 (Cont'd)
XCZU7EV
(U1) Pin
AC12 DDR4_SODIMM_WE_B
AD14 DDR4_SODIMM_ACT_B
AF13 DDR4_SODIMM_ALERT_B
AC13 DDR4_SODIMM_PARITY
AD12 DDR4_SODIMM_CS0_B
AM13 DDR4_SODIMM_CS1_B
AF12 DDR4_SODIMM_RESET_B
The ZCU104 board PL DDR4 SODIMM interface adheres to the constraints guidelines
documented in the "PCB Guidelines for DDR4" section of UltraScale Architecture PCB Design
User Guide (UG583)
implementation. Other memory interface details are also available in the UltraScale
Architecture FPGAs Memory Interface Solutions Product Guide (PG150)

PSMIO

Table 3-5 provides PS MIO peripheral mapping implemented on the ZCU104 board. See the
Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085)
on PS MIO peripheral mapping.
Table 3-5: MIO Connections
ZU7EV
MIO
U1
[25:0] Schematic Net Name
Pin
Bank 500
No.
MIO25 D29 MIO25_CAN_RX
MIO24 E28 MIO24_CAN_TX
MIO23 B29 Not Connected
MIO22 F28 Not Connected
MIO21 C28 UART1_TXD_MIO21_RXD
MIO20 E29 UART1_RXD_MIO20_TXD
MIO19 B28 UART0_RXD_MIO19_TXD
MIO18 F27 UART0_TXD_MIO18_RXD
MIO17 C29 MIO17_I2C1_SDA
MIO16 A28 MIO16_I2C1_SCL
MIO15 E27 Not Connected
MIO14 A27 Not Connected
MIO13 D27 Not Connected
MIO12 C27 Not Connected
MIO11 B26 Not Connected
MIO10 F26 Not Connected
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
Net Name I/O Standard
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
LVCMOS12
[Ref 4]. The PL DDR4 SODIMM interface is a 40Ω impedance
MI ZU7EV
[51:26] U1
Type Schematic Net Name
Bank Pin
501 No.
CAN MIO51 F34 MIO51_SDIO_CLK_R
CAN MIO50 F33 MIO50_SDIO_CMD_R
NC MIO49 F32 MIO49_SDIO_DAT3_R
NC MIO48 F31 MIO48_SDIO_DAT2_R
UART1 MIO47 F30 MIO47_SDIO_DAT1_R
UART1 MIO46 E34 MIO46_SDIO_DAT0_R
UART0 MIO45 E33 MIO45_SDIO_DETECT
UART0 MIO44 E32
I2C1 MIO43 E30
I2C1 MIO42 D34
NC MIO41 D32
NC MIO40 D31
NC MIO39 D30
NC MIO38 C34
NC MIO37 C33
NC MIO36 C32
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Chapter 3: Board Component Descriptions
DDR4 SODIMM Memory J1
Pin Number
151
114
116
143
149
157
108
MIO
Type [77:52]
Bank 502
SD1 MIO77
SD1 MIO76
SD1 MIO75
SD1 MIO74
SD1 MIO73
SD1 MIO72
SD1 MIO71
Not Connected NC MIO70
Not Connected NC MIO69
Not Connected NC MIO68
Not Connected NC MIO67
Not Connected NC MIO66
Not Connected NC MIO65
Not Connected NC MIO64
Not Connected NC MIO63
Not Connected NC MIO62
Pin Name
WE_N/A14
ACT_N
ALERT_N
PARITY
CS0_N
CS1_N
RESET_N
[Ref 5].
[Ref 2] for more information
ZU7EV
U1
Schematic Net Name
Pin
No.
L34 MIO77_ENET_MDIO
L33 MIO76_ENET_MDC
L30 MIO75_ENET_RX_CTRL
L29 MIO74_ENET_RX_D3
K34 MIO73_ENET_RX_D2
K33 MIO72_ENET_RX_D1
K32 MIO71_ENET_RX_D0
K31 MIO70_ENET_RX_CLK
K30 MIO69_ENET_TX_CTRL
K29 MIO68_ENET_TX_D3
K28 MIO67_ENET_TX_D2
J34 MIO66_ENET_TX_D1
J32 MIO65_ENET_TX_D0
J31 MIO64_ENET_TX_CLK
J30 MIO63_USB_DATA7_R
J29 MIO62_USB_DATA6_R
Send Feedback
Type
MDIO3
MDIO3
GEM3
GEM3
GEM3
GEM3
GEM3
GEM3
GEM3
GEM3
GEM3
GEM3
GEM3
GEM3
USB0
USB0
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