Psmio - Xilinx ZCU111 User Manual

PSMIO

Table 3-2 provides PS MIO peripheral mapping implemented on the ZCU111 board. See the
Zynq UltraScale+ Device Technical Reference Manual (UG1085)
on PS MIO peripheral mapping.
Table 3-2: MIO Peripheral Mapping
MIO[0:25] Bank 500
0 QSPI
1 QSPI
2 QSPI
3 QSPI
4 QSPI
5 QSPI
6 Not assigned/no connect
7 QSPI
8 QSPI
9 QSPI
10 QSPI
11 QSPI
12 QSPI
13 GPIO
14 I2C0
15 I2C0
16 I2C1
17 I2C1
18 UART0
19 UART0
20 Not assigned/no connect
21 Not assigned/no connect
22 GPIO
23 GPIO
24 Not assigned/no connect
25 Not assigned/no connect
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
Chapter 3: Board Component Descriptions
MIO[26:51] Bank 501
26 PMU IN
27 DPAUX
28 DPAUX
29 DPAUX
30 DPAUX
31 Not assigned/no connect
32 PMU OUT
33 PMU OUT
34 PMU OUT
35 PMU OUT
36 PMU OUT
37 PMU OUT
38 GPIO
39 SD1
40 SD1
41 SD1
42 SD1
43 Not assigned/no connect
44 Not assigned/no connect
45 SD1
46 SD1
46 SD1
48 SD1
49 SD1
50 SD1
51 SD1
www.xilinx.com
[Ref 3] for more information
MIO[52:77] Bank 502
52 USB0
53 USB0
54 USB0
55 USB0
56 USB0
57 USB0
58 USB0
59 USB0
60 USB0
61 USB0
62 USB0
63 USB0
64 GEM3
65 GEM3
66 GEM3
67 GEM3
68 GEM3
69 GEM3
70 GEM3
71 GEM3
72 GEM3
73 GEM3
74 GEM3
75 GEM3
76 MDI03
77 MDI03
Send Feedback
26