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SINGLE
COMPONENT
SYSTEM
First
SEL ANO
.Starts
conversion
of
ANO
input
Conversion
MOV
R0,#24
;Set
up
memory
pointer
50
us
RAD
;First
conversion
value
to
4 bytes
accumulator
Second
MOV
@R0,A
;Store
first
conversion value
Conversion
INCRO
;lncrement
memory
location
40
ms
RAD
;Second conversion
value
to
3 bytes
accumulator
Note
that
the
second
conversion occurs
without
a
second
select
instruction
being used. Rather, the
continuous operation
of
the
A/D
converter
pro-
vides
an updated
digital
value
4
instruction
cycles
after
the
first.
To
insure
maximum
accuracy from
the
A/D
con-
verter,
separate
power
supply
pins
(AVcc
and
AVss) and
a
substrate
pin
(SUBST) have
been
provided. Supplying the
power
supply
pins with
a
well
filtered
and
regulated voltage supply
mini-
mizes
the
effect of
power
supply variance
and
system
noise.
The
substrate
pin
should
be
by-
passed
to
ground through a
500 pF
to
0.001
ixF
capacitor.
2.19
CPU
The
8022
CPU
has
arithmetic
and
logical capabili-
ty.
There
is
a wide
variety
of
arithmetic
and
logic
instructions
which
affect
the contents
of
the accu-
mulator,
and
/or
direct
or
indirect
scratchpad
lo-
cations.
Provisions
have been
made
for simplified
BCD
arithmetic capability using the
DAA,
SWAP
A,
and
XCHD
instructions.
In
addition,
MOVP
A,@A
allows
table
lookup
for
display formating
and
constants.
The
conditional
branch
logic within
the
processor enables
several conditions
internal
and
external
to
the
processor
to
be
tested
by
the
user's
program.
Use
the
conditional
jump
instruc-
tions
with the tests
listed
below
to effect
a
change
in
the
program
execution
sequence.
Test
Jump
Conditio n
Jump
Instructions
A=0
A^O
JZ
JNZ
1
JNC,
JC
—
1
JTF
1
JNT1, JT1
1
JNTO,
JTO
Accumulator
Carry Flag
Timer Overflow Flag
Test
lnput-T1
Test Input-TO
2.20
8022
Testing
and Debug
To
facilitate
testing
and
debug,
certain test
modes
may
be
activated
in
the
8022
by
raising
combina-
tions of
RESET,
TEST
1
and
PROG
to
15
volts.
Internal
ROM
is
dumped
out sequentially
for
verifi-
cation.
External
memory
operation
is
used
for
CPU
checkout.
Function
Power On
Clear
Normal
Operation
On
each
cycle
internal
ROM
is
dumped
to
Port
—
sequentially
after
ALE
leading
edge.
On
every
TEST
1
falling
edge
the
program
counter
incre-
ments,
dumps
internal
ROM
to
Port
Chip
will
operate from
external
memory
(one
page)
via
Port
0.
ALE
strobes
Address
out,
mem-
ory
in.
Chip accepts op
codes
into
Port
1.
Allows
Port
and
8243
testing.
Reset
Prog
Test
1
Case
5V
X
X
OV
X
X
15V
15V
15V
Mode
1a
15V
15V
-TT_
Mode
1b
15V
Mode
3
NOTE
X
=
Normal
mode
-
between
OV
and
Vqc
2-30
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