Intel MCS48 User Manual page 374

Family of single chip microcomputers
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irrtJ
8291
GPIB TALKER/LISTENER
Designed
to
Interface
Microprocessors
(e.g.,
8080, 8085, 8086, 8048)
to
an
IEEE Standard 488
Digital
Interface
Bus
Programmable
Data
Transfer Rate
Complete Source and Acceptor
Handshake
Complete
Talker
and
Listener
Functions
with
Extended Addressing
Service Request,
Parallel
Poll,
Device
Clear,
Device
Trigger,
Remote/Local
Functions
Selectable
Interrupts
On-Chip
Primary
and Secondary
Address
Recognition
Automatic Handling
of
Addressing
and
Handshake
Protocol
Provision
for
Software Implementation
of
Additional Features
1
-8 MHz
Clock
Range
16 Registers
(8
Read,
8
Write),
2
for
Data
Transfer, the
Rest
for
Interface
Function
Control, Status,
etc.
Directly Interfaces to
External
Non-
Inverting
Transceivers
for
Connection
to
the
GPIB
Provides
Three Addressing Modes,
Allowing
the
Chip
to
be Addressed
Either
as a
Major
or a
Minor
Talker/
Listener with
Primary
or
Secondary
Addressing
DMA
Handshake
Provision
Allows
for
Bus
Transfers without
CPU
Intervention
Trigger
Output
Pin
On-Chip
EOS
(End
of
Sequence)
Message
Recognition
Facilitates
Handling
of
Multi-Byte Transfers
The
8291
GPIB
Talker/Listener
is
a microprocessor-controlled chip designed
to interface
microprocessors
(e.g.,
8048,
8080, 8085, 8086)
to
an IEEE Standard 488 Instrumentation
Interface
Bus.
It
implements
all
of
the Standard's
interface
functions except
for
the
controller.
PIN
CONFIGURATION
BLOCK DIAGRAM
TR/lC
1
TR/2C
2
CLOCK
C
3
RESETC
4
TRIGC
5
DMAREQC
6
DMA
ACKL"
7
CSt
8
SEC
9
WffC
10
intL"
11
DOC
12
D1C
13
D2C
14
D3C
15
D4C
16
D5C
17
D6C
18
D7C
19
VssC
20
8291
Dvcc
3EOI
NDAC
NRFD
DAV
DI08
DI07
5156
DDI05
DI04
35T03
HDI02
3DI01
3SRQ
DATN
I]
REN
JVfc
3RS2
3
RSI
HRS0
o
REGI
3EAD
REGISTERS
c
c
8
WRITE
REGISTERS
o
:>
INTERFACE
FUNCTIONS
n
MESSAGE
DECODER
/fc
T/R
CONTROL
>
TO NON-INVERTING
BUS TRANSCEIVERS
INTEL
CORPORATION ASSUMES
NO
RESPONSIBILITY
FOR
THE USE OF
ANY
CIRCUITRY
OTHER THAN
CIRCUITRY
EMBODIED
IN
AN
INTEL
PRODUCT.
NO
OTHER
CIRCUIT
PATENT
LICENSES ARE
IMPLIED.
©
INTEL
CORPORATION, 1979
3.34
00229A

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