Intel MCS48 User Manual page 153

intgl
8048/8648/8748/8035
SINGLE
COMPONENT
8-BIT
MICROCOMPUTER
•
8048
Mask
Programmable
ROM
•
8648 One-Time
Factory
Programmable
EPROM
•
8748 User Programmable/Erasable
EPROM
•
8035/8035L
External
ROM
or
EPROM
8-Bit
CPU,
ROM, RAM,
I/O
in
Single
Package
Interchangeable
ROM
and
EPROM
Versions
Single 5V Supply
2.5
Msec and
5.0
Msec Cycle
Versions
All
Instructions
1
or 2 Cycles.
Over
90
Instructions:
70%
Single
Byte
1Kx 8ROM/EPROM
64
x 8
RAM
27
I/O Lines
Interval
Timer/Event Counter
Easily
Expandable
Memory
and
I/O
Compatible
with 8080/8085 Series
Peripherals
Single Level
Interrupt
The
Intel® 8048/8648/8748/8035
is
a
totally self-sufficient, 8-bit parallel
computer
fabricated
on
a
single silicon chip
using
Intel's
N-channel
silicon gate
MOS
process.
The
8048 contains a
1
K x
8
program memory,
a
64 x
8
RAM
data
memory,
27
I/O lines,
and an
8-bit
timer/counter
in
addi-
tion to
on-board
oscillator
and clock
circuits.
For
systems
that require extra capability, the 8048 can be expanded
using standard memories and MCS-80™/MCS-85™
peripherals.
The 8035
is
the equivalent of
an 8048
without program
memory. The 8035L
has the
RAM
power-down
mode
of
the
8048
while the
8035 does
not.
The
8648
is
a one-time
pro-
grammable
(at
the
factory)
8748 which can be
ordered as the
first
25 pieces
of a
new
8048
RAM
order.
The
substitution
of 8648's
for
8048's allows
for
very
fast
turnaround
for
initial
code
verification
and
evaluation
units.
To
reduce
develop-
ment
problems
to
a
minimum
and
provide
maximum
flexibility,
three interchangeable pin-compatible versions
of
this
single component microcomputer
exist:
the
8748
with user-programmable and
erasable
EPROM
program
memory
for
prototype and
preproduction systems, the 8048
with factory-programmed
mask
ROM
program
memory
for
low
cost,
high
volume
production,
and
the 8035 without
program memory
for
use
with external
program memories.
This microprocessor
is
designed
to
be an
efficient controller
as
well
as an arithmetic processor. The
8048 has
exten-
sive
bit
handling
capability as
well
as
facilities
for both binary
and
BCD
arithmetic. Efficient use
of
program
memory
results
from an
instruction set
consisting
mostly
of single byte instructions
and no
instructions over 2 bytes
in
length.
PIN
CONFIGURATION
XTAL
1[
XTAL
2
(
RESETl
C
2
L
3
SST
5
INTC
6
EA[
7
SbC
s
PSENC
9
wfiC
u
aleC h
°B
C
i;
db,[I
i:
DB
2
C
1<
OB
3
C
1!
DB
4
C
If
DBsC
1;
DB6C
If
OB,C
1!
v ssC
21
8048
8648
8748
8035
moN
L(
)GIC
SYMBOL
DVcc
XTAL
—
r__
OCxr
I]P26
_
—
*
3P25
UP2«
RESET
CO-
RT
I)P16
SINGLE
STEP
*
.-READ
UP15
D
P14
EXTERNAL
^
MEM
"
8048
U Pt3
p
„
WRITE
DP12
TEST-
]P11
]P10
-—
PROGRAM
STORE
ENABLE
Hv
0D
INTERRUPT
I]
PROG
3P23
DP22
UP21
DP20
BUS<^
t>
ADDRESS
LATCH
ENABLE
PORT
EXPANDER
STROBE
BLOCK DIAGRAM
INTEL CORPORATION ASSUMES NO
RESPONSIBILITY FOR THE USE OF ANY
CIRCUITRY OTHER THAN CIRCUITRY EMBODIED
IN
AN
INTEL PRODUCT.
NO
OTHER
CIRCUIT
PATENT
LICENSES ARE IMPLIED
c
INTEL CORPORATION, 1979
„
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