Intel MCS48 User Manual page 148

APPLICATION
EXAMPLES
16x8
DIVIDE-(ASSEMBLED BY MCS-48
MACRO
ASSEMBLER
SEE
AP-49)
ISIS-II MCS-48/'UPI-41 MACRO ASSEMBLER,
V3
SOURCE STATEMENT
B04B
2A
004C 8B08
004E
37
B04F
61
0050
37
0053
m7
0054 046F
0057
97
0058
2A
005?
F7
B05A
2A
005B
F7
005C E66
B05E
37
005F
61
0060
37
0061 046
0063
37
0064
61
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
21
1
212
213
214
2
15
216
217
21 8
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
*INCLUDE<
:
Fl
:
DIV16
)
I.****.**********************************************************************'
THIS
UTILITY PROVIDES
AN
16
BY
8
UNSIGNED DIVIDE
AT
ENTRY:
A
=
LOWER EIGHT BITS OF
DESTINATION OPERAND
XA =
UPPER EIGHT BITS OF
DIVIDEND
Rl=
POINTER TO
DIVISOR
IN
INTERNAL MEMORY
AT
EXIT
:
A
=
LOWER EIGHT BITS OF
RESULT
XA =
REMAINDER
C
= SET
IF
OVERFLOW ELSE CLEARED
**************** *******************
»»*********»****«»*«»*******»***»*•*»»**"
1
DIV16:
DI
V16
:
XCH
A, XA
;l
COUNT:
= 8
MOV
COUNT,
#8
; 1
DIVIDEND! 15-8I:=DIVIDEND[ 15-8] -DIVISOR
CPL
A
ADD
A
,
8R1
CPL
A
il IF
BORROW=0 THEN
/*
IT
FITS*/
J C
D
I
V
I
A
;2
SET OVERFLOW FLAG
CPL
C
J
M P
D
I
V
I
8
il
ELSE
DIVIA
:
)2
RESTORE DIVIDEND
ADD
A,
SRI
;2
REPEAT
DI
V
ILP
ROUTINE WORKS MOSTLY WITH BITS
15-8
;4
01
V
IE
:
CLR
XCH
RLC
XCH
RLC
JNC
CPL
ADD
CPL
J
MP
CPL
ADD
DIVIDEND
:
=DIVIDEND*2
QUOTIENT :=QU0TIENT»2
C
A
,
XA
A
A
,
XA
A
DI
VIE
A
A,
AR1
DI
VIC
DIVIDENDC15-8].'=DIVIDENDtl5-83-DIVIS0R
5-28