Intel MCS48 User Manual page 388

8291
Using
DMA
The
8291
may
be connected
to the
Intel
8257
DMA
Con-
troller for
DMA
operation.
The
DMA
REQ
pin of
the 8291
requests a
DMA
byte transfer from
the 8257.
It
is
set by
BO
or
Bl flip flops,
masked
by the
DMAO
and DMAI
bits
in
the
Interrupt
Mask
2 Register.
(After reading, the INT1
register
BO
and
Bl interrupts
will
be cleared but not
BO
and
Bl
in
DREQ
equation.)
The
DMA
ACK
pin
is
driven
by
t
he 8257
in
response
to
the
DMA
request.
When
DMA
ACK
is
true (active low)
it
sets
CS
= RSO =
RS1
= RS2 =
such
that
the
RD
and
WR
signals sent by the 8257
refer to
the Data
In
and
Dat
a
Out
Regis
ters. Also, the
DMA
request
line
is
reset
by
DMA
ACK.
DMA
input
sequence:
1.
A
data byte
is
accepted from
the
GPIB
by the 8291.
2.
A
Bl interru pt
is
generated and
DMA
REQ
is
set.
3.
DMA
ACK
is
asserted by
the
8257 and
DMA
REQ
is
reset.
4.
RD
is
driven by the
8257 and
the contents
of
the
Data
In
Register are transferred
to
MCS
bus.
5.
The
8291 sends
RFD
true on
the
GPIB
and proceeds
with the Acceptor
Handshake
protocol.
DMA
output sequence:
1.
A
BO
interrupt
is
generated
(indicating that the
Data
Out
Register
is
empty) and
DMA
REQ
is
asserted.
2.
DMA
ACK
is
asserted by the 8257
and
DMA
REQ
is
rese
t.
3.
WR
is
driven
by
the
8257 and
a byte
is
transferred
from
the
MCS
bus
into the
Data Out
Register.
4.
The
8291 sends
DAV
true
on
the
GPIB
and proceeds
with
the
Source
Handshake
protocol.
It
should be noted
that
each time the device
is
addressed,
the Address
Status Register should be
read,
and
the
8257
should be
initialized
accordingly. (Refer
to
the
8257
data
sheet available
in Intel's
Peripheral
Design Handbook.)
System
Configuration
Microprocessor Bus Connection
The
8291
is
8080, 8048,
8085 and 8086
compatible.
The
three
address
pins (RSo, RSi, RS2) should be connected
to
the non-multiplexed address bus
(for
example:
As, Ag,
A10).
In
case
of 8080,
any
address
lines
may
be
used.
External Transceivers
Connection
8291
IEEE bus
pins are
TTL
compatible. For
IEEE
Std.
bus
connection,
external transceivers are required. 8291
supplies Transmit/Receive
control
pins:
T/R1
controls
DIO1-8,
NRFD,
NADC
and
DAV
transceivers,T/R2
controls
EOI
transceiver. IFC,
ATN,
REN
are
always
inputs
and
SRQ
is
always an
output.
Logically,
TR1
= TACS
+
SPAS +
PPAS;
TR2 =
TACS +
SPAS.
Refer to
8292 Data Sheet
for
8291/8292 system
configuration.
8-98
00229A