Intel MCS48 User Manual page 466

Family of single chip microcomputers
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HEXADECIMAL INSTRUCTION
CODES
ACCUMULATOR
•ADD
A,R
r
6*
ADD
A,@R0
60
R1
61
ADD
A,#data
03
ADDC
A,R
r
7*
ADDC
A,@R0
70
R1
71
ADDC
A,#data
13
ANL
A,R
r
5*
ANL
A,@RO
50
R1
51
ANL
A,#data
53
ORL
A,R
r
4*
ORL
A,@R0
40
R1
41
ORL
A,#data
43
XRL
A,R
r
D*
XRL A,@R0
DO
R1
D1
XRL
A,#data
D3
INC
A
17
DEC
A
07
CLR
A
27
CPL
A
37
RL
A
E7
RLC
A
F7
RR
A
77
RRC
A
67
DA
A
57
SWAP
A
47
DATA MOVES
MOV
A,R
r
F*
MOV
A,
fa
RO
F0
R1
F1
MOV
A,#data
23
MOV
R
r
,
A
A.
MOV
@R0,A
A0
R1,A
A1
MOV
R
r
,#data
B*
MOV
@R0,#data
B0
R1,#data
B1
XCH
A,R
r
2*
XCH
A,@R0
20
R1
21
XCHD
A,@R0
30
R1
31
MOV
A.PSW
C7
MOV
PSW.A
D7
MOVX
A,@R0
80
R1
81
MOVX
@R0,A
90
R1.A
91
MOVP3
A,@A
E3
MOVP
A,@A
A3
REGISTER
INC
R
r
DEC
R
r
INC
@R0
R1
DJNZ
R
r
,
addr
FLAGS
•CLR
C
•CPL C
CLR
F0
CPL
F0
CLR
F1
CPL
F1
BRANCH
JMP
addr
JMPP
@A
DJNZ
R
r
,addr
JC
addr
JNC
addr
JZ
addr
JNZ
addr
JT0
addr
JNTO
addr
JT1 aadr
JNT1
addr
JFO
addr
JF1 addr
JTFaddr
JNI addr
JBO
addr
JB1 addr
JB2
addr
JB3
addr
JB4
addr
JB5
addr
JB6
addr
JB7addr
TIMER
MOV
A,T
MOV
T,A
STRT
T
STRT
CNT
STOP TCNT
EN
TCNTI
DIS
TCNTI
1*
c*
10
11
E*
97
A7
85
95
A5
B5
t4
B3
E*
F6
E6
C6
96
36
26
56
46
B6
76
16
86
12
32
52
72
92
B2
D2
F2
42
62
55
45
65
25
35
CONTROL
EN
I
05
DIS
I
15
SEL
RBO
C5
SEL
RB1
D5
SEL
MBO
E5
SEL
MB1
F5
ENTO CLK
75
SUBROUTINE
CALL
addr
f4
RET
83
RETR
93
°
RETI
93
NO OP
NOP
00
input/output:
IN
A,P1
09
OUTL
P1,A
39
ANL
P1,#data
99
ORL
P1,
#data
89
IN
A,
P2
OA
OUT
L P2,
A
3A
ANL
P2,
#data
9A
ORL
P2,#data
8A
INS
A,
BUS
08
OUTL
BUS,
A
02
ANL
BUS,
#data
98
ORL
BUS,
#data
88
movda.pp
o:
MOVD
Pp,A
3*.
ANLD
Pp,A
9*.
ORLD
Pp,A
8*.
°
OUTL
Po,A
90
°
IN A,
Po
08
A/D
°
SEL
AN0
85
°
SEL AN1
95
°
RAD
80
=
Carry
Flag Affected
=
See
Table
1
=
8021 or
8022
only
See
Table
2
See
Table
3

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