Are - Intel MCS48 User Manual

Family of single chip microcomputers
Hide thumbs Also See for MCS48:
Table of Contents

Advertisement

8259A
INTERRUPT
SEQUENCE
OUTPUTS
MCS-80/85
SYSTEM
This
sequ ence
is
timed by
three
INTA
pulses.
During the
first
INTA
pulse the
CALL
opcode
is
enabled onto
the
data
bus.
Content
of First Interrupt
Vector Byte
CALL
CODE
During the
second INTA
pulse
the lower
address
of
the
appropriate service routine
is
enabled onto the data
bus.
When
Interval
=
4
bits
A
5
-A
7
are
programmed,
while
A
-
A
4
are
automatically inserted by the
8259A.
When
Inter-
val
=
8 only
A
6
and
A
7
are
programmed,
while
A
-A
5
are
automatically
inserted.
Content
of
Second
Interrupt
Vector Byte
D7
06
OS
04
D3
D2
D1
DO
1
1
1
1
1
IR
Interval*
4
D7
D8
OS
D4
D3
D2
D1
00
7
A7
A6
A5
1
1
1
6
A7
A6
A5
1
1
5
A7
A6
A5
1
1
4
A7
A6
A5
1
3
A7
A6
A5
1
1
2
A7
A6
A5
1
1
A7
A6
A5
1
A7
A6
A5
IR
Interval
k
8
D7
D6
D5
04
03
02
01
00
7
A7
A6
1
1
1
6
A7
A6
1
1
5
A7
A6
1
1
4
A7
A6
1
3
A7
A6
1
1
2
A7
A6
1
1
A7
A6
1
A7
A6
During the
third
INTA
pulse the higher
address
of
the
appropriate service
routine,
which
was programmed
as
byte
2
of
the
initialization
sequence
(A
8
-A
15
),
is
enabled onto
the bus.
Content
of
Third
Interrupt
Vector Byte
D6
OS
04
03
02
D1
00
A14
A13
A12
A11
A10
A8
MCS-86
SYSTEM
MCS-86
mode
is
similar to
MCS-80
mode
except
that
only
two
Interrupt
Acknowledge
cycles are issued by
the
processor
and no
CALL
opcode
is
sent
to
the
proc-
essor.
The
first
interrupt
acknowledge
cycle
is
similar to
that of
MCS-80/85 systems
in
that
the
8259A
uses
it
to
internally
freeze the state
of
the
interrupts
for priority
resolution
and
as a master
it
issues
th
e
inte rrupt
code
on
the
cascade
lines at
the
end
of the
INTA
pulse.
On
this
first
cycle
it
does
not issue
any
data
to
the
proc-
essor
and
leaves
its
data
bus
buffers disabled.
On
the
second
interrupt
acknowledge
cycle
in
MCS-86
mode
the
master
(or
slave
if
so
programmed)
will
send
a byte
of
data
to
the
processor
with the
acknowledged
inter-
rupt
code
composed
as
follows (note the state
of the
ADI
mode
control
is
ignored
and
As-A^
are
unused
in
MCS-86
mode):
Content
of Interrupt
Vector Byte
for
MCS-86 System
Mode
D7
D6
DS
D4
03
D2
D1
00
IR7
A15
A14
A13
A12
A11
1
1
1
IR6
A15
A14
A13
A12
A11
1
1
IR5
A15
A14
A13
A12
A11
1
1
IR4
A15
A14
A13
A12
A11
1
IR3
A15
A14
A13
A12
A11
1
1
IR2
A15
A14
A13
A12
A11
1
IR1
A15
A14
A13
A12
A11
1
IRO
A15
A14
A13
A12
A1
8-46

Advertisement

Table of Contents
loading

Table of Contents