Intel MCS48 User Manual page 234

8185/8185-2
OPERATIONAL
DESCRIPTION
The
8185 has been designed
to provide
for direct interface
to
the multiplexed bus
structure
and bus
timing
of
the
8085A
microprocessor.
At the beginning
of
an 8185
memory
access
cycle^Jhe
8-
bit
address on
ADo-7,
Ae and
Ag,
and
the status
of
CEi and
CE2
are
all
latched
internally
in
the 8185 by
the
falling
edge
of
ALE.
If
the latched status
of
both CEi and
CE2
are
actiyjMhe
81
85 powers
itself
up, but
no
action
occurs
until
the
CS
line
goes low and
the appropriate
RD
or
WR
control
signal input
is
activated.
The
CS
input
is
not latched by
the
8185
in
order
to
allow
the
maximum
amount
of
time
for
address decoding
in
selecting the
8185
chip.
Maximum
po wer
c
onsumption
savings
will
occur,
however, only
when
CEi and CE2
are
activated selectively
to
power down
the
81
85
when
it
is
not
in
use.
A
possible
connec
tion
would be
to
wire the 8085A's
IO/M
line
to the 8185's CEi
input,
thereby keeping the
8185
powered
down
during
I/O
and
interrupt cycles.
TABLE
1.
TRUTH
TABLE FOR
POWER DOWN
AND
FUNCTION ENABLE
c^
CE
2
CS
(CS*)l
2
l
8185
Status
1
X X
Power
Down
and
Function Disable^]
X X
Power
Down
and
Function Disables
]
1
1
Powered Up
and
Function
Disablefi]
1
1
Powered
Up
and
Enabled
Notes:
X:
Don't Care.
1:
Function Disable
implies
Data Bus
in
high
impedance
state
and
not
writing.
2:
CS* =
(CEi
=
0)
•
(CE
2
=
1
)
.
(CS
=
0)
CS*
=
1
signifies
all
chip enables and
chip
select active
TABLE
2.
TRUTH
TABLE FOR
CONTROL AND DATA
BUS
PIN
STATUS
(CS*)
RD
WR
AD
_
7
During Data
Portion
of
Cycle 8185
Function
X
X
Hi-Impedance No
Function
1
1
Data from
Memory
Read
1 1
Data
to
Memory
Write
1
1
1
Hi-Impedance
Reading, but not
Driving
Data Bus
Note:
X:
Don't Care.
HDh,
TRAP
RST7.5
RST6.5
RST5.5
INTR
TNTA
8085A
HOLD
HLDA
SOD
SID
RESET
,.
ADDR/
JDUT
ADDR
DATA ALE RD WR
IO/M
RDY
CLK
7\
C
c
c
00
PORT
'8156
B
IO/M
TIMER
o
C
<.
E
t
OUT
<x>
;>
8355/
8755A
DATA/
ADDR
IO/M
pQR
RESET
RDY
CLK
<^
<x>
mr
V
S S
V
cc
V DD PROG
>
'8185
ALE
CS,
CE
2
As.
A
Q
Figure
1.
8185
in
an MCS-85
System.
4 Chips:
2K
Bytes
ROM
1.25K Bytes
RAM
38
I/O Lines
1
Counter/Timer
2 Serial I/O Lines
5 Interrupt Inputs
6-82