Intel MCS48 User Manual page 354

8278
TO TONE GENERATOR
,
8085
OR
8048
MASTER
PROCESSOR
16
DIGIT
SCAN
Figure
1.
System
Configuration
for
Capacitive-Coupled
Keyboard
Keyboard Debounce
and
Control
The
8278 system
configuration
is
shown
in
Figure
2.
The
rows
of the matrix are scanned and
the outputs are
multiplexed by
the 8278.
When
a
key
closure
is
detected,
the
debounce
logic waits
about
1
2
msec
to
check
if
the key
remains
closed.
If it
does.the address
of the key
in
the
matrix
is
transferred
into a
FIFO
buffer.
FIFO and FIFO
Status
The
8278
contains an
8X8 FIFO
character
buffer.
Each
new
entry
is
written into a successive
FIFO
location
and
each
is
then read out
in
the order
of entry.
A
FIFO
status
register
keeps
track
of
the
number
of characters
in
the
FIFO and whether
it
is full
or empty.
Too many
reads or
key
entries
will
be recognized
as
an
error.
The
status
can
be read
by a
RD
with
CS
low
and Ao
high.
The
status logic
also provides a
IRQ
signal to the master processor
whenever
the
FIFO
is
not empty.
Display
Address
Registers
and
Display
RAM
The
display
Address
registers hold the address
of
the
word
currently being written or read by
the
CPU
and
the
4-bit
nibble
being
displayed.
The
read/write
addresses
are
programmed
by
CPU
command.
They
also
can be
set
to
auto increment
after
each
read
or
write.
The
display
RAM
can be
directly read
by
the
CPU
after
the correct
mode
and address
is
set.
Data entry to the display can
be
set to either
left
or right entry.
8080. 8085
OR
8048
MASTER"
PROCESSOR
c
-V
TO TONE GENERATOR
ERROR
CLR
.) D
-D
7
8278
Jv
-16---
16
DIGIT
SCAN
CONTACT
KEYBOARD
MATRIX
8
OR
16
DIGIT
DISPLAY
Figure
2.
System
Configuration
for
Contact Keyboard
8-64
00227A