Intel MCS48 User Manual page 243

inur
2111A
256
x
4 BIT
STATIC
RAM
2111A-2 250
ns
Max.
2111A
350 ns Max.
2111A-4 450
ns
Max.
Common
Data
Input
and Output
Single
+5V Supply
Voltage
Directly
TTL
Compatible:
All
Inputs
and
Output
Static
MOS: No
Clocks
or Refreshing
Required
Simple
Memory
Expansion: Chip Enable
Input
Fully
Decoded:
On
Chip Address
Decode
Inputs Protected:
All
Inputs
Have
Pro-
tection
Against
Static
Charge
Low
Cost Packaging:
18
Pin Plastic
Dual
In-Line Configuration
Low
Power:
Typically 150
mW
Three-State Output:
OR-Tie
Capability
The
Intel® 21
1 1
A
is
a
256 word
by
4-bit static
random
access
memory
element
using N-channel
MOS
devices
integrated
on
a
monolithic
array.
It
uses
fully
DC
stable
(static) circuitry
and
therefore requires
no
clocks or refreshing
to
operate.
The
data
is
read out nondestructively
and
has the
same
polarity
as the input
data.
Common
input/output pins are provided.
The 2111A
is
designed
for
memory
applications
in
small
systems where
high performance, low
cost,
large
bit
storage,
and
simple
interfacing are important design
objectives.
It
is
directly
TTL
compatible
in
all
respects: inputs, outputs,
and
a single
+5V
supply.
Separate chip enable (CE)
leads allow
easy
selection of an
individual
package when
outputs
are OR-tied.
The
Intel® 21
1
1
A
is
fabricated with
N-channel
silicon
gate technology. This technology allows the design and
production
of
high performance, easy-to-use
MOS
circuits
and
provides a higher functional density
on
a monolithic chip than
either
conventional
MOS
technology
or
P-channel
silicon
gate technology.
Intel's
silicon gate
technology
also provides excellent protection against contamination. This permits the use
of
low
cost
plastic
packaging.
PIN
CONFIGURATION
LOGIC SYMBOL
a
3
[Z
1
A
2
[Z
Ao[Z
A
5
C
A
6
(Z 6
A7[Z
GND
|
Vcc
Z1a
4
Ir/w
Z]CE,
Z]l/0
4
Z]i/o
3
I]
I/O,
ZJCEj
PIN
NAMES
A
-A
7
ADDRESS
INPUTS
OD
OUTPUT
DISABLE
I
R/W READ/WRITE INPUT
CHIP
ENABLE
1
'
CE
2
CHIP
ENABLE
2
l/O-t-l/04
DATA
INPUT/OUTPUT
:
BLOCK DIAGRAM
INTEL CORPORATION ASSUMES NO
RESPONSIBILITY FOR THE
USE
OF ANY
CIRCUITRY OTHER THAN
CIRCUITRY
EMBODIED
IN
AN
INTEL PRODUCT. NO OTHER
CIRCUIT
PATENT
LICENSES ARE
IMPLIED
O
INTEL
CORPORATION, 1979
7-5