Intel MCS48 User Manual page 385

8291
Auxiliary
Mode
Register 4-Bit
Code
CNT2 CNT1 CNTO
COM4 COM3 COM2 COM1 COMO
AUX MODE
(5W)
CNTO—
2:CONTROL
BITS
COMO—
:COMMAND
BITS
The
Auxiliary
Mode
Register contains a three-bit control
field
and
a five-bit
command
field.
It
is
used
for several
purposes on the 8291:
1.
To
load
"hidden"
auxiliary registers
on
the 8291.
2.
To
issue
commands
from
the
microprocessor
to the
8291.
3.
To
preset
an
internal
counter used
to
generate T1,
delay
in
the
Source
Handshake
function,
as defined
in
IEEE
488.
Table 4
summarizes
how
these
tasks are
performed
with
the Auxiliary
Mode
Register.
Note
that the three control
bits
determine
how
the
five
command
bits
are
interpreted.
TABLE
4
CODE
CONTROL
BITS
COMMAND
BITS
COMMAND
000
001
100
101
011
occcc
0FFFF
DDDDD
0DDDD
USP3P2P1
Execute
auxiliary
command
CCCC
Preset
internal
counter
to
match
external clock
frequency
of
FFFF
MHZ
(FFFF
-
binary representation
of
1
to
8
MHz)
Write
DDDDD
into auxiliary
register
A
Write
DDDD
into auxiliary
register
B
Configure/unconfigure
parallel poll
SP3P2P1
as
defined
in
Std. 488.
(Con-
figure
if
U =
0,
Unconfigure
if
U =
1
).
This
command
is
the
local poll
enable
(Ipe)
message when
U =
0.
AUXILIARY
COMMANDS
Auxiliary
commands
are
executed by the 8291
whenever
0000CCCC
is
written into the Auxiliary
Mode
Register,
where
CCCC
is
the
4-bit
command
code.
4-Bit
Code
0000
Description
Immediate Execute pon
—
This
command
re-
sets
the
8291
to
a
power up
state (local
pon
message as defined
in
IEEE
488).
The following conditions constitute the
power
up
state:
1.
All
talkers
and
listeners are disabled.
2.
No
interrupt status
bits
are
set.
0010
0011
0100
0101
0110
0111, 1111
0001, 1001
Description
The
8291
is
designed
to
power up
in
certain
states
as specified
in
the
IEEE 488
state dia-
grams. Thus, the following
states are
in
effect
in
the
power up
state:
SIDS, AIDS, TIDS, LIDS,
NPRS, LOCS,
and PPIS.
The "0000" pon
is
an immediate execute
command
(a
pon
pulse).
It
is
also
used
to
release the
"initialize"
state
generated by
either
an
external
reset
pulse or the "0010"
Chip Reset
command.
Chip
Reset
(Initialize)
—
This
command
has
the
same
effect
as a pulse applied to the
Reset
pin.
(Refer to
the section
on
Reset Procedure.
)
Finish
Handshake
—
This
command
finishes a
handshake
that
was
stopped because
of a
holdoff
on
RFD
or
DAV.
(Refer to Auxiliary
Register
A.)
Trigger
—
A
"Group Execute
Trigger"
is
forced by
this
command.
It
has the
same
effect
as a
GET command
issued
by the
controller-
in-charge
of
the
GPIB,
but
does
not
cause
a
GET
interrupt.
rtl
1
—
This
command
corresponds
to the local
rtl
message
as defined
in
IEEE
488.
The
8291
will
go
to a local state
if
local
lockout
is
not
in
effect.
Send EOI
—
The
EOI
line of
the 8291
may
be
asserted with this
command. The
command
causes EOI
to
go
true with
the next byte
trans-
mitted.
The
EOI
line is
then cleared
upon com-
pletion of the
handshake
for that byte.
Non-Valid/Valid
Secondary Address
or
Command
(VSCMD)
—
This
command
in-
forms the 8291
that
the
secondary address
re-
ceived
by
the
microprocessor
was
valid
or
invalid (0111
-
invalid,
1111 -valid).
If
Mode3
addressing
is
used, the
processor must
field
each extended address and respond
to
it,
or
the
GPIB
will
hang
up.
Note
that
the
COM3
bit
is
the invalid/valid
flag.
The
valid
(1111)
command
is
also
used
to
tell
the 8291
to
continue from
the
command-pass-
through
state
(immediate execute
command).
Parallel Poll
Flag
(local "ist"
message)
—
This
command
sets (1001) or clears (0001)
the
parallel
poll flag.
A "1"
is
sent over the
assigned
data
line
(PPR-Parallel
Poll
Re-
sponse
true)
only
if
the
parallel poll flag
matches
the
sense
bit
from
the Ipe
local
message
(or indirectly
from
the
PPE
mess-
age).
For
a
more
complete
description
of
the
Parallel Poll
features
and procedures
refer to
the section
on
Parallel Poll Protocol.
1.
Subsequently the 8291
will
include
"set
rtl"
and
"clear
rtl"
commands.
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00229A