Intel MCS48 User Manual page 306

8253/8253-5
Read
Operations
In
most
counter
applications
it
becomes
necessary
to
read
the value
of the count
in
progress and
make
a
computational
decision based on
this quantity.
Event
counters
are probably
the
most
common
application
that
uses
this
function.
The
8253
contains
logic that
will
allow
the
programmer
to easily read the contents
of
any
of
the
three
counters without
disturbing the actual
count
in
progress.
There
are
two methods
that
the
programmer
can use
to
read the value
of the counters.
The
first
method
involves
the use
of
simple
I/O read operations
of
the selected
counter.
By
controlling the AO, A1
inputs
to
the 8253 the
programmer
can
select the counter
to
be read
(remember
that
no
read operation
of the
mode
register
is
allowed
AO,
A1-11).
The
only
requirement
with
this
method
is
that
in
order
to
assure
a stable
count reading
the actual operation
of the selected counter must
be
inhibited either by
controlling the Gate
input or by
external logic that inhibits
the clock
input.
The
contents
of the counter selected
will
be
available as follows:
first
I/O
Read
contains
the
least
significant byte (LSB).
second
I/O
Read
contains the most
significant
byte
(MSB).
Due
to the internal logic of
the
8253
it
is
absolutely
necessary
to
complete
the
entire
reading procedure.
If
two
bytes are
programmed
to
be read then two
bytes
must be
read before any
loading
WR
command
can be
sent
to
the
same
counter.
Read
Operation Chart
A1 AO
RD
Read Counter
No.
1
Read Counter
No.
1
1
Read Counter
No.
2
1
1
Illegal
Reading While Counting
In
order
for the
programmer
to read the contents
of
any
counter without
effecting or disturbing the
counting
operation the
8253 has
special
internal logic that
can be
accessed
using simple
WR
commands
to
the
MODE
register. Basically,
when
the
programmer
wishes
to
read
the contents
of a selected
counter "on
the
fly"
he loads the
MODE
register with a special
code which
latches the
present count
value
into a
storage
register
so
that
its
contents
contain an
accurate, stable
quantity.
The
programmer
then
issues a
normal
read
command
to
the
selected counter and
the contents
of the latched
register
is
available.
MODE
Register
for
Latching Count
AO,
A1
=
11
D7 D6
D5 D4 D3
D2
D1 DO
SC1 SCO X
X X
X
SC1.SC0—
specify counter
to
be
latched.
D5.D4
—
00 designates counter
latching operation.
X
—
don't
care.
The
same
limitation
applies to this
mode
of
reading the
counter as the previous method. That
is,
it
is
mandatory
to
complete
the
entire read operation as programmed.
This
command
has no
effect
on
the counter's
mode.
CLK
8085
3MHz
2
*
1.5MHz
CLK
8253-5
*lf
an 8085
clock output
is
to drive
an
8253-5 clock
input,
it
must
be reduced
to
2
MHz
or
less.
Figure
8.
MCS-85™
Clock
Interface*
8-16
00745A