Intel MCS48 User Manual page 309

8253/8253-5
Clock
and Gate
Timing:
SYMBOL PARAMETER
8253
MIN.
MAX.
8253-5
MIN.
MAX.
UNIT
tfJLK
Clock Period
380
dc
380 dc
ns
tPWH
High
Pulse
Width 230 230
ns
tPWL
Low
Pulse
Width
150 150
ns
tGW
Gate Width High 150 150
ns
tGL
Gate
Width
Low
100 100
ns
*GS
Gate
Set
Up
Time
to
CLKt
100 100
ns
tGH
Gate Hold Time
After
CLKt
50 50
ns
*OD
Output Delay
From CLK-M
1
'
400
400
ns
tQDG
Output
Delay
From
Gatei'
1
!
300 300
ns
Note
1:
Test Conditions:
8253:
Cl=
100pF;
8253-5:
C|_= 150pF.
_,
I>WL-
»<OD—
^\
u
X
8-19
00745A