Intel MCS48 User Manual page 339

8259A
OPERATION
COMMAND WORDS
(OCWs)
After the
Initialization
Command
Words
(ICWs) are
pro-
grammed
into
the 8259A, the chip
is
ready to
accept
interrupt
requests
at
its
input
lines.
However, during the
8259A
operation, a selection of algorithms
can com-
mand
the
8259A
to
operate
in
various
modes
through
the
Operation
Command
Words
(OCWs).
OPERATION
CONTROL
WORDS
(OCWs)
m
07
M
OCW1
D5 D4 D3 D2
01 00
|
M7
M6
M5
M4 M3 M2 M1 MO
|
OPERATION
CONTROL
WORD
1
(0CW1)
0CW1
sets
and
clears the
mask
bits
in
the
interrupt
Mask
Register
(IMR).
M
7
- M
represent the eight
mask
bits.
M
=
1
indicates the channel
is
masked
(inhibited),
M =
indicates the
channel
is
enabled.
OPERATION
CONTROL
WORD
2
(OCW2)
R,
SEOI, EOI
—
These
three bits
control the Rotate
and
End
of Interrupt
modes
and combinations
of
the two.
A
chart of
these combinations can be found on the Opera-
tion
Command
Word
Format.
L
2
,
Li,
Lq
—
These
bits
determine
the interrupt
level
acted
upon
when
the
SEOI
bit is
active.
m
m
SEOI
EOI
SRIS
RIS
OPERATION
CONTROL
WORD
3
(0CW3)
ESMM
—
Enable
Special
Mask
Mode.
When
this
bit is
set to
1 it
enables the
SMM
bit
to set or reset the Special
Mask
Mode.
When
ESMM
=
the
SMM
bit
becomes
a
"don't care".
SMM
—
Special
Mask
Mode.
If
ESMM
=
1
and
SMM
=
1
the
8259A
will
enter Special
Mask
Mode.
If
ESMM
=
1
and
SMM
=
the
8259A
will
revert to
normal
mask mode.
When
ESMM
=
0,
SMM
has no
effect.
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