Model; Intellec Series - Intel MCS48 User Manual

MODEL
230
FUNCTIONAL
DESCRIPTION
Hardware
Components
The
Intellec Series
II
Model
230
is
a packaged, highly
integrated microcomputer development system
consist-
ing of a
CRT
chassis
with a
6-slot
cardcage, power
sup-
ply, fans,
cables,
and
five printed
circuit cards.
A
separate,
full
ASCII keyboard
is
connected
with a
cable.
A
second
chassis contains two
floppy disk
drives capa-
ble of double-density operation along with a separate
power
supply,
fans,
and
cables
for
connection
to the
main
chassis.
A
block diagram
of the
Model 230
is
shown
in
Figure
1.
CPU
Cards
—
The
master
CPU
card contains
its
own
microprocessor, memory,
I/O, interrupt
and bus
inter-
face
circuitry fashioned from
Intel's
high technology
LSI
components.
Known
as the integrated
processor board
(IPB),
it
occupies
the
first slot
in
the cardcage.
A
second
slave
CPU
card
is
responsible
for
all
remaining
I/O
con-
trol
including the
CRT
and keyboard
interface. This
card,
mounted
on
the rear panel, also
contains
its
own
micro-
processor,
RAM
and
ROM
memory, and
I/O interface
logic, thus,
in effect, creating a dual
processor
environ-
ment.
Known
as the
I/O
controller
(IOC), the slave
CPU
card
communicates
with the IPB over an
8-bit bidirec-
tional
data
bus.
Memory
and
Control Cards
—
In
addition,
32K
bytes
of
RAM
(bringing the
total
to
64K
bytes)
is
located
on
a
separate card
in
the
main
cardcage. Fabricated from
Intel's
16K RAMs,
the board
also contains
all
necessary
address decoding and
refresh
logic.
Two
additional
boards
in
the
cardcage
are
used
to control the
two
double-density floppy disk
drives.
Expansion
—
Two
remaining
slots
in
the
cardcage
are
available
for
system
expansion.
Additional expansion
of
4 slots
can be achieved
through
the addition of an
Intel-
lec Series
II
expansion
chassis.
System Components
The
heart of the IPB
is
an
Intel
NMOS
8-bit
microproces-
sor,
the 8080A-2, running
at 2.6
MHz. 32K
bytes
of
RAM
memory
are provided
on
the board using
Intel
16K
RAMs. 4K
of
ROM
is
provided,
preprogrammed
with
sys-
tem
bootstrap
"self-test"
diagnostics and
the
Intellec
Series
II
System
Monitor.
The
eight-level
vectored
prior-
ity interrupt
system
allows
interrupts to
be
individually
masked.
Using
Intel's versatile
8259
interrupt controller,
the
interrupt
system
may
be user
programmed
to
respond
to individual needs.
INTERRUPT
CONTROL
BAUD RATE
GENERATOR
A
REAL
TIME
CLOCK
ii.
T7" Tf
ii.
TT
T>
TT
ii.
Tf
Figure
1.
Intellec Series
II
Model 230 Microcomputer Development System
Block Diagram
9-6