Intel MCS48 User Manual page 321

8255A/8255A-5
CONTROL
WORD
D
7
D„
D
5
D
4
D
3
D
2
D
1
D
1
1
/\/\/\
1/0 1/0 1/0
—
1
- INPUT
0« OUTPUT
PORTB
1
=
INPUT
=
OUTPUT
GROUP
B
MODE
=
MODE
1
-
MODE
1
Figure
11.
MODE
Control
Word
Figure
12.
MODE
2
PERIPHERAL
BUS
DATA
FROM
CPU TO
82S5A
I
"<t_>-
DATA FROM
PERIPHERAL TO
8255A
\
r
DATA
FROM
j
8255A
TO
PERIPHERAL
/
DATA
FROM
82SSA
TO
8080
Figure
13.
MODE
2
(Bidirectional)
NOTE: Any
sequence where
WR
occurs before
ACK
and
STB
occurs before
RD
is
permissible.
(INTR = IBF
•
MASK
•
STB
•
RD
+
OBF
•
MASK
•
ACK
•
WR
)
8-31
00744A